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  HEPHY logbook for testbeam at SPS June 2009, Page 3 of 6  Not logged in ELOG logo
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Entry  Sat Aug 22 13:30:28 2009, Christian Irmler, BELLE, internal calibration 31.8 MHz transparent mode (cooling?), cal008, , 22.08.2009 12:50:48, 22.08.2009 13:29:25 
Belle DUT, intcal
HV=80V, 31.8 MHz, beam off
1 sample, transparent mode
Entry  Sat Aug 22 13:28:53 2009, Wolfgang Kiesenhofer, Pt_ITE512, runlist for pt-module angle-scan, , , ,  
Preliminary run list for pt-modules + ite512 + silc1, silc2, silc5, silc6

    
        
            run
            angle[deg]
            
Entry  Sat Aug 22 12:12:34 2009, Christian Irmler, BELLE, internal calibration 40 MHz transparent mode (cooling?), cal007, , 22.08.2009 12:10:32 , 22.08.2009 12:49:09 
Belle DUT, intcal
HV=80V, 40 MHz, beam off
1 sample, transparent mode
Entry  Sat Aug 22 11:54:49 2009, Thomas Bergauer, common, beam profile, , , ,  20090822_1150_beam_conditions.jpg
beam shifted a bit in vertical direction downwards since 21. August 09 evening
Beam configuration:
Beam configuration file: H6b.802 (FM HAD (P0 off, H8=+180) PARLALLEL IN H6B SILC 2008
Entry  Sat Aug 22 11:26:00 2009, Thomas Bergauer, BELLE, APVDAQ + telescope 40 MHz hit mode (cooling?), run018, 75k, 22.08.2009 11:16:57, 22.08.2009 11:58:56 
 HV=80V, 40 MHz, beam on, 120 GeV
6 samples, hit mode, hitcut=5
chiller set to 13 deg.
 

f=40
Entry  Sat Aug 22 10:28:50 2009, Thomas Bergauer, BELLE, APVDAQ + telescope 40 MHz hit mode (cooling?), run017, 75k, 22.08.2009 10:26:28, 22.08.2009 11:16:12 
 HV=80V, 40 MHz, beam on, 120 GeV
6 samples, hit mode, hitcut=4
chiller set to 13 deg.
 

f=40
Entry  Sat Aug 22 09:44:50 2009, Thomas Bergauer, BELLE, APVDAQ + telescope 31,8 MHz hit mode (cooling?), run016, 75k, 22.08.2009 09:42:38, 22.08.2009 10:24:05 
 HV=80V, 31.8 MHz, beam on, 120 GeV
6 samples, hit mode, hitcut=5
chiller set to 13 deg.
 

f=31.8
Entry  Sat Aug 22 08:32:02 2009, Thomas Bergauer, BELLE, APVDAQ + telescope 31,8 MHz hit mode (cooling?), run015, 75k, 22.08.2009 08:15:05, 22.08.2009 09:25:21 
 HV=80V, 31.8 MHz, beam on, 120 GeV
6 samples, hit mode, hitcut=4
chiller set to 13 deg.
 

f=31.8
Entry  Sat Aug 22 03:27:13 2009, Thomas Bergauer, BELLE, APVDAQ + telescope 31,8 MHz transparent mode (cooling?), run014, 75k, 22.08.2009 03:25:23, 22.08.2009 07:08:09 
 HV=80V, 31.8 MHz, beam on, 120 GeV
6 samples
chiller set to 13 deg.
 

f=31.8 MHz
Entry  Sat Aug 22 01:06:34 2009, Christian Irmler, BELLE, APVDAQ + telescope 40 MHz transparent mode (cooling?), run013, 75000, 21.08.2009 23:49:38 , 22.08.2009 03:21:48 
Belle DUT, tranparent mode
HV=80V, 40 MHz, beam on, 120 GeV
6 samples
Entry  Fri Aug 21 22:42:32 2009, Thomas Bergauer, common, EUDAQ config file used when running with telescope, , , ,  testfortis_with_eudrb_beam_backpressure_WITH_SILC.conf


 
Used until Friday, 21.08.09:
Entry  Fri Aug 21 18:35:13 2009, Christian Irmler, BELLE, APVDAQ + telescope 31.8 MHz transparent mode, run012, 60000, 21.08.2009 18:31:01, 21.08.2009 23:25:03 
4 Belle DUTs
HV=80V, 31.8 MHz, 6 sample, 120 GeV
external clock source
Entry  Fri Aug 21 18:07:57 2009, Christian Irmler, BELLE, APVDAQ standalone 31.8 MHz, pedcorr004, , 21.08.2009 17:49:10, 21.08.2009 18:24:31 
4 Belle DUTs
HV=80V, 31.8 MHz
pedestal correction
Entry  Fri Aug 21 17:14:58 2009, Wolfgang Kiesenhofer, , S/N Histograms Raw (no data selection), run001 (strips), run002 (pitch adapter), run003 (upper edge), , ,  sn_langaufit_raw_strips.pdfsn_langaufit_raw_pa.pdfsn_langaufit_raw_edgerun.pdf
 
Entry  Fri Aug 21 16:37:22 2009, Christian Irmler, BELLE, internal calibration 40 MHz hit mode, cal006, , 21.08.2009 16:30:33,  
Belle DUT, intcal
HV=80V, 40 MHz, no beam
hit mode
Entry  Fri Aug 21 15:27:08 2009, Christian Irmler, BELLE, internal calibration 31.8 MHz hit mode, cal005, , 21.08.2009 15:34:43, 21.08.2009 16:29:47  
Belle DUT, intcal
HV=80V, 31.8 MHz, no beam
hit mode
Entry  Fri Aug 21 14:18:11 2009, Christian Irmler, BELLE, internal calibration 31.8 MHz transparent mode, cal004, , 21.08.2009 14:21:40, 21.08.2009 15:01:24 
Belle DUT, intcal
HV=80V, 31.8 MHz, no beam
transparent mode
Entry  Fri Aug 21 13:38:20 2009, Christian Irmler, BELLE, APVDAQ standalone 31.8 MHz hit mode, run011, 75000, 21.08.2009 13:35:25 ,  
4 Belle DUTs
HV=80V, 31.8 MHz, 6 sample, 120 GeV
external clock source
Entry  Fri Aug 21 12:22:43 2009, Christian Irmler, BELLE, APVDAQ standalone 31.8 MHz hit mode, run010, 75000, 21.08.2009 12:53:02, 21.08.2009 13:35:01 
4 Belle DUTs
HV=80V, 31.8 MHz, 6 sample, 120 GeV
switched to external clock source
Entry  Fri Aug 21 12:08:44 2009, Christian Irmler, BELLE, APVDAQ standalone 40 MHz, pedcorr003, , 21.08.2009 12:08:33, 21.08.2009 12:18:45  
4 Belle DUTs
HV=80V, 40 MHz
pedestal correction 
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