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  HEPHY logbook for testbeam at SPS June 2008, Page 3 of 4  Not logged in ELOG logo
ID Date Author Project Subject Run Number Events StartTime EndTime
  26   Sun Jun 1 15:08:17 2008 Markus FriedlSiLCAPVDAQ only (0-sup)run000310000001.06.2008 15:05:5101.06.2008 15:33:58
SiLC beam test - CERN SPS June 2008 - HIT MODE
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-2.75 mm
trigger: 9 mm opening, TLUControl.exe -d 2 -a 12 (manually)
no telescope

This is MID position
APVDAQ runs in HIT MODE (=0-suppressed)
acquisition rate ~300 Hz during spill
  25   Sun Jun 1 15:02:51 2008 Markus FriedlSiLCAPVDAQ onlyped0031000001.06.2008 15:00:5401.06.2008 15:04:14
SiLC beam test - CERN SPS June 2008 - PEDESTAL with beam
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-2.75 mm
software trigger
no telescope

PEDESTAL WITH BEAM (10k) @ MID
  24   Sun Jun 1 14:58:53 2008 Markus FriedlSiLCAPVDAQ onlyped0021000001.06.2008 14:55:3101.06.2008 14:59:06
SiLC beam test - CERN SPS June 2008 - PEDESTAL
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-7.5 mm
software trigger
no telescope

PEDESTAL with BEAM (10k events) @ LEFT
  23   Sun Jun 1 14:36:23 2008 Markus FriedlSiLCAPVDAQ only (0-sup)run000210000001.06.2008 14:25:4301.06.2008 14:54:14
SiLC beam test - CERN SPS June 2008 - HIT MODE
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-7.5 mm
trigger: 9 mm opening, TLUControl.exe -d 2 -a 12 (manually)
no telescope

This is LEFT position
APVDAQ runs in HIT MODE (=0-suppressed)
acquisition rate ~300 Hz during spill
  22   Sun Jun 1 08:06:57 2008 stephan hänselSiLCAPVDAQ + telescope (raw)run2721-27372200001.06.2008 - 08:01:5301.06.2008 - 14:19:13
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-7.5 mm
trigger: 9 mm opening, TLUControl.exe -d 10 -a 12
telescope: raw, new firmware

horizontal position ("target") = -7.5mm
this is LEFT position
  21   Sun Jun 1 01:56:47 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run272010000001.06.2008 01:51:4501.06.2008 07:48:09
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-7.5 mm
trigger: 9 mm opening, TLUControl.exe -d 10 -a 12
telescope: zero supressed, new firmware

horizontal position ("target") = -7.5mm
this is LEFT position
  20   Sat May 31 22:54:29 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run271910000031.05.2008 22:34:3801.06.2008 01:49:30
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=-2.75 mm
trigger: 9 mm opening, TLUControl.exe -d 10 -a 12 (now for real)
telescope: zero supressed, new firmware

horizontal position ("target") = -2.75mm
this is MID position
  19   Sat May 31 18:33:50 2008 Thomas Bergauerotherbeam profile    
Beam configuration
Beam configuration file: H6b.802 (FM HAD (P0 off, H8=+180) PARLALLEL IN H6B SILC 2008

Rate: 5.7E5 particles/spill (measured with SCINT8 in beamline)

Particle Production Applet
Calculator applet

For +120 Gev/c beam:

Pi+55.67 %
p38.95 %
K+ 5.38 %
Attachment 1: Picture_1.png
Picture_1.png
Attachment 2: beamline_settings.png
beamline_settings.png
  18   Sat May 31 17:36:14 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run271810000031.05.2008 16:21:5731.05.2008 21:08:32
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor stage :=+2 mm
trigger: 9 mm opening, TLUControl.exe -d 10 -a 12 (now for real)
telescope: zero supressed, new firmware

- long break in the middle due to power outage after thunderstorm

horizontal position ("target") = +2.0mm - after we decided to scan the whole area in 3 steps
this is RIGHT position

all 3 positions are:
RIGHT: +2.00 mm    <--- this run
MID:   -2.75 mm
LEFT:  -7.50 mm
  17   Sat May 31 17:32:35 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup) run2717649031.05.2008 15:57:5831.05.2008 16:09:21
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples
trigger: 9 mm opening, TLUControl.exe -d 10 -a 12 (now for real)
telescope: zero supressed, new firmware

trigger is now correct (9 x 9 mm2 window)
horizontal position ("target") = 0.0mm
  16   Sat May 31 17:29:40 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run27162000031.05.2008 14:59:2631.05.2008 15:56:23
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples
trigger: 9 mm opening, TLUControl.exe -d 10 -a 12
telescope: zero supressed, new firmware

in fact, trigger was set to coincidence of ALL FOUR scintillators, hence only (less than) 4 x 4 mm2 window !!!
horizontal position ("target") = 0.0mm
  15   Sat May 31 13:34:28 2008 Thomas Bergauer how to copy data from lab2pc to eudetmac    
rsync -rltvz --exclude "data_vie" --exclude "hitfit_cern08" --exclude "output_vie" --exclude "run2719*" --rsh="ssh -C -p222" friedl@routerhephy.cern.ch:/cygdrive/f/testbeam/cern_jun08/ /Volumes/Data/eudet/APVDAQ/

but replace run2719 with the name of the run file currently active (data taking)

and use Markus' password
  14   Fri May 30 19:42:13 2008 stephan hänselSiLCAPVDAQ onlyrun00015180330.05.2008 19:38:0430.05.2008 22:54:59
SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples
trigger: 9 mm opening, TLUControl.exe -d 2 -a 12
no telescope

terminated after 51803 events due to beam drop out @ 22.00h
  12   Fri May 30 10:36:18 2008 Marko DragicevicotherImportant Information/Contact    
IPs
Linksys Router
  • external: routerhephy.cern.ch (137.138.171.102)
  • internal: 192.168.1.1
    US&ER /PA_SS'WD: admin/sensor
  • WLAN-SSID: HEPHY
  • WLAN-WPA-TKIP: testbeam08

EUDETMAC
  • external: eudetmac001.cern.ch
  • U1SE*R/P*AS§S/WD (ssh): eudet/gsigsi
  • from EUDETMAC to TLU:
    ssh tlupc

LAB2PC (APVDAQ, DUT HV)
  • internal: 192.168.1.10
  • external VNC: routerhephy.cern.ch (137.138.171.102:5900)
    pa2s2s2w2d: hephy

XY Table
  • internal VNC: 192.168.1.11
    pa2s2s2w2d: hephy

Beam Control PC
  • external VNC: CWO-HNA453-H6B1.CERN.CH (137.138.61.206)

Phone
Vienna CERN Mobile Phone (usually Thomas Bergauer)
  • 162471

Daniel Haas
  • 165423

Marko Dragicevic
  • Hostel (39-120): 79 120
  • Private: +43 650 4243343

Markus Friedl
  • Hostel (41-107): 60 107
  • Private: +43 699 17251085

Thomas Bergauer
  • Hostel (39-220): 79 220
  • Private: +43 664 3769400 (switched off during testbeam)

Christian Irmler
  • Hostel (41-222): 60 222
  • Private: +43 699 19437327

Misc
SPS Page 1

Path to start cesar
  11   Mon May 26 15:38:53 2008 Markus FriedlSiLCHow to run APVDAQ    
Power-on Procedure
==================

PC logon: user "testbeam", pwd "sensor"

Order for switching on the hardware (not strict):
* VME 9U crate
* keithley instruments
* +-5V (fat) 2 lab power supplies (left stack)
* other 3 lab power supplies (right stack)
    BE CAREFUL NOT TO CHANGE DIALS AT ALL DURING SWITCHING!!!

Run ResMan.exe (shortcut on desktop) and click OK to close
Start longterm-R31.vi (shortcut on desktop) and start HV bias
Start APVDAQ.exe 

Now everything is on and ready to operate.
This is also the condition after a run is finished.


Start Run (see screenshot below)
================================

1. select proper run type (if different from previous run), typically
 Hardware (beam) or
 Software (pedestal) or
 Internal Calibration

2. open proper config file (if different from previous run), one of
 cern08_silc_all_single.cfg   (8 DUTs, 1 sample)  - for software (pedestal) and intcal runs
 cern08_silc_all_multi6.cfg   (8 DUTs, 6 samples) - for hardware (beam) runs

 cern08_silc_mod03_single.cfg (1 DUT, module 03, 1 sample)  - for software (pedestal) and intcal runs
 cern08_silc_mod03_multi6.cfg (1 DUT, module 03, 6 samples) - for hardware (beam) runs
 

3. select file name (typically: increase run number)

4. switch Write File ON (if turned off)

5. write some useful comments (conditions, HV, etc)

6. enter number of events

7. hit "Start Run" and relax or cry for help :-)


Additional Info
===============

path to APVDAQ:   e:\cvi-projects\apvdaq_fadc
path to Longterm: e:\labview-projects\longterm R3.1
path to data:     f:\testbeam\cern_jun08\silc\data
Attachment 1: panel_instruction.gif
panel_instruction.gif
Attachment 2: cern08_silc_all_single.cfg
# 40 mhz
# single peak mode (1 sample)
# 50ns peaking time
# 30ns trigger window (built from 5ns window, thus ~12.5ns later)
# NECO
#
# Data processing with FADC+PROC
# SPS Testbeam - full setup
# FADC 0  four hybrids
# FADC 1  four hybrids
#
#
# CI 07 may 2008
#
#
# Lines preceded by a # or ; sign are ignored.
#
# [rem] comments a whole section until the next section start marked by [xxx] .
#

# [vme]
# VME addresses are given in the format
#  {module_name} = {vme_module_number},{vme_address_hex}
#  nec ... NECO module
#  adf ... particular FADC module
#
# Please note that the address ranges are not defined here,
# they are implicitly given by the hardware.
# Module numbers must fill from 0 (this is not checked).
# Please note that no range checking is performed.
# There is no access to VME modules that are not included in this list,

[vme]
nec = 0,0x1a000000

adf = 0,0x1b000000
adf = 1,0x2b000000

# [nec]
# NECO related information
#  mod = 0|1,{shift_register_delay},{adc_range},{win_delay},{win_length},{dead_time},{time_lat},{max_trg}
#          (default: 0,75,0,50?,900?,36,2,1)
#  res = {list of entries in reset sequence}                (default: 2,4)
#  cal = {list of entries in cal sequence}			(default: 2,3,250,251)
#  sw5 = {list of entries in single cal sequence}		(default: 2,3)
#  str = {list of entries in software trigger sequence}		(default: 75)
#  htr = {list of entries in hardware trigger sequence}		(default: 74)
#
# mod specifies to use either the sequencer (0) or the shift register (1) for hardware trigger and the
#  delay of the shift register (0..255); adc_range (0=1Vpp, 1=2Vpp) -- ignored; win_delay and win_length define
#  the starting point (relative to the APV trigger) and length of the ADC gate in transparent mode; dead_time is
#  the number of 254MHz clock cycles which are set to zero for time measurement after an incoming trigger;
#  time_lat is the latency for time measurement in terms of 40MHz clock cycles; max_trg is the number of incoming
#  triggers which required to activate the veto logic (usually 1; 0 completely disables the veto logic)
# res, cal, sw5, str and htr are containing the bits to set in the 256-element sequencer memory (nothing is set at -1)
# Please note that cal+str together produce a calibration request plus subsequent normal trigger, so the time
#  between them is the latency. sw5 is used to send a single cal request to achieve the correct polarity in
#  case the APV inverter is turned on (this feature only works for entire MAMBOs halves = groups of 3 REBOs)
# 
# These settings are quite fragile! Do not modify until you know exactly what you are doing.

[nec]

# 30m cables, 40mhz, Tp=50ns, single-trigger 
#mod = 0,75,0,70,250,36,2,1
#htr = 61,-1,-1,-1,-1,-1,-1,-1
#str = 100,-1,-1,-1,-1,-1,-1,-1

# TESTBEAM Nov 07, 30m cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 59,62,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1

# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, single-trigger (1 samples)
mod = 0,75,0,70,250,36,2,1
htr = 63,-1,-1,-1,-1,-1,-1,-1
str = 100,-1,-1,-1,-1,-1,-1,-1

# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 61,64,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1


#common settings
res =  2, 4, -1, -1,-1,-1,-1,-1
cal =  2, 3,250,251,-1,-1,-1,-1
sw5 =  2, 3, -1, -1,-1,-1,-1,-1




# [daq]
# DAQ related specifications are given in the format
#  ads = {N},{search_max_subevents},0,x
#  ini = {initevents},{readout_mode},0,x
#  deh = {module_position},{apv_position},0,x
#  i2t = {N},0,0,x
#  pat = 0,0,0,{data_file_path}
#  clk = {N},{Delay25 frequency range},0,x
#  pdl = {Trigger input delay},0,0,x
#  crd = {crate_number},{clkdel},{trgdel},x
#
# ads N gives the number of samples that are read out from the FIFO1 in transparent mode, search_max_subevents is the
#  maximum number of subevents to search for within one ADC stream (default=1).
# ini: initevents is the number of software triggers in the beginning of a run for pedestal and noise
# evaluation. At the beginning of each run, 2*initevents are generated by software, after that the 
# selected trigger source (hardware, software of calibration) is activated. The initial evaluation
# events are written to disk as normal events are.
# ini: readout_mode defines whether events beyond the initevents are read in raw transparent mode from FIFO1 (0) or
#  in processed mode (1) where only hit information is read from FIFO3
# deh is the APV chip for which single strip histograms are recorded
# i2t is the maximum number of I2C retries in case of failure
# pat specifies the save path for data files (must include a trailing backslash!)
# clk gives the system clock period in integer ns (25 max.) and the frequency range for the Delay25 chip:
#  0...40 MHz, 1...80 MHz, 2...32 MHz, 3...64 MHz
# pdl specifies the delay setting for the trigger input in 0.5ns steps (0..49)
# crd define the global clock and trigger delays between NECO and SVD3_buffer for crates 0 and 1
#  NOTE: clock and trigger is NOT propagated to any crate(s) NOT specified here


[daq]

# TESTBEAM Nov 07
#Standard
ads = 250,1,0,x

# TESTBEAM Nov 07
#Multitrigger (6)
#ads = 950,6,0,x

# RAW (transparent mode) readout
ini = 300,0,0,x

# PROCESSED readout
#ini = 300,1,0,x

deh = 1,0,0,x
i2t = 5,0,0,x
pat = 0,0,0,F:\\testbeam\\cern_jun08\\silc\\data\\

#standard 40mhz clock (25ns)
clk = 25,0,0,x
pdl = 25,0,0,x

#crate distribution delays (set to mid-range to allow adjustments in both directions)
crd = 0,25,25,x

#we don't use crate 1, so we don't set any delay here -> no clock/trigger to crate 1
###crd = 1,25,25,x


# [hit]
# Hit recognition variables are specified here
#  hcs = {hitcut_seed_strip},{hitcut_neighbor_strips}
#  nok = {x.x},0
#  
#
# hcs gives seed and neighbor hit cuts in units of strip sigma
# nok states the threshold over average noise at which strips are excluded from further analysis (to exclude noisy strips)

[hit]
# si sensor
hcs = 4.0,4.0

# do not exclude strips
nok = 2000.0,0


# [cal]
# Calibration related data
#  lvl = {level},0
#  lat = {latbeg},{latend}
#  sam = {average_samples},{number of samples in 6-tuple mode}
#  grp = {number_of_groups},0
#  lg6 = {latency},{group}
#  lv6 = {startlevel},{endlevel}
#
# lvl is the CLVL amplitude (0..255), 1 is 625e-, 36 is 1 MIP (22500e-) nominally, in reality 26 is 1 MIP
# lat is the Latency range to cover (latend-latbeg>=2, latend-latbeg<=15)
# sam is the number of samples to average per position for normal and 6-tuple modes
# grp is how many groups to scan (<=8), first group is strips 0,8,16,..., second group is 1,9,17,..., ...
# lg6 defines the latency in 6-tuple mode and which group to observe in that mode
# lv6 defines the scan range of amplitude in 6-tuple mode

[cal]
#real 1 MIP level (22400e)
lvl = 26,0

#real 5 MIPs level
#lvl = 130,0

#LAT=95/98 Calibration (short display)
#lat = 89,100

#LAT=95/98 Calibration (short display for >=50mhz)
#lat = 81,98

#LAT=95/98 Calibration (long peak mode tail display)
lat = 75,100

#common settings
sam = 50,150
grp = 8,0

#6-tuple mode settings
lg6 = 97, 1
#lv6 =  1,95
lv6 =  50,52




# [i2c]
# This section defines one or more I2C sets for the APV25. In the [mod] section, those sets are referenced to by their number.
#  ia2 = {number},{mode},{lat},{ipre},{ipcasc},{ipsf},{isha},{issf},{ipsp},{imuxin},{vfp},{vfs},{vpsp},{muxgain}
#
# The I2C settings must be individually numbered (ascending from 0). The easiest case is to use the same
# settings for all chips of one type, but one could go so far to use separate settings for each chip.
# vadj/vpsp is set individually for each apv in the [mod] section, the value specified here is meaningless.

[i2c]

# apv25s1, peak, inverter ON, Tp=50ns, (p side)
ia2 =          0,    63,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, peak, inverter OFF, Tp=50ns, (n side)
ia2 =          1,    31,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# apv25s1, multi-peak, inverter ON, Tp=50ns, (p side)
#ia2 =          0,    61,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side)
#ia2 =          1,    29,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# [mod]
# Detector module (actually hybrid) specifications are given in the format
#  mod = {module_position},{crate_number},{mambo_number},{rebo_number},{hybrid_number},m,{AD8128_peak},{rebo_clkdelay},{rebo_trgdelay},0,0,0,0,{Name}
#  apv = {module_position},{apv_position},{i2c_address},{i2c_settings},{vadj/vpsp},x,0,0,{fadc_offset},{fadc_number},{fadc_channel},{fadc_clkdelay [0..49]},{AD8128_gain},x
#
# mod gives the hybrid/module properties: The position counts from 0 to 7 in beam direction,
#  Name must not contain blanks ("_" is allowed).
# apv describes the chips located on a hybrid 
#  and the ADC channel where they are read out, either a Vienna ADC (a) or a FED (f).
# The ADC offset is only available with the Vienna ADCs and shifts the baseline.
# The individual chip vadj setting dominates over the [i2c] setting.


[mod]

# module 0
mod = 0,0,0,2,0,m,45,25,0,0,0,0,0, 0_SiLC_05/05
apv = 0,0,36,0,30,x,0,0,5,0,1,12,100,x
apv = 0,1,38,0,30,x,0,0,5,0,2,15,100,x
# module 1
mod = 1,0,0,2,1,m,45,25,0,0,0,0,0, 1_SiLC_07/07
apv = 1,0,36,0,30,x,0,0,5,0,5,15,100,x
apv = 1,1,38,0,30,x,0,0,5,0,6,16,100,x
# module 2
mod = 2,0,0,2,2,m,45,25,0,0,0,0,0, 2_SiLC_06/03
apv = 2,0,36,0,30,x,0,0,5,0,9,10,100,x
apv = 2,1,38,0,30,x,0,0,5,0,10,15,100,x
# module 3
mod = 3,0,0,2,3,m,45,25,0,0,0,0,0, 3_SiLC_04/04
apv = 3,0,36,0,30,x,0,0,5,0,13,12,100,x
apv = 3,1,38,0,30,x,0,0,5,0,14,14,100,x
# module 4
mod = 4,0,1,1,0,m,45,25,0,0,0,0,0, 4_SiLC_03/10
apv = 4,0,36,0,30,x,0,0,110,1,1,14,100,x
apv = 4,1,38,0,30,x,0,0,110,1,2,15,100,x
# module 5
mod = 5,0,1,1,1,m,45,25,0,0,0,0,0, 5_SiLC_12/08
apv = 5,0,36,0,30,x,0,0,110,1,5,14,100,x
apv = 5,1,38,0,30,x,0,0,110,1,6,16,100,x
# module 6
mod = 6,0,1,1,2,m,45,25,0,0,0,0,0, 6_SiLC_10/02
apv = 6,0,36,0,30,x,0,0,110,1,9,12,100,x
apv = 6,1,38,0,30,x,0,0,120,1,10,15,100,x
# module 7
mod = 7,0,1,1,3,m,45,25,0,0,0,0,0, 7_SiLC_20/09
apv = 7,0,36,0,30,x,0,0,125,1,13,10,100,x
apv = 7,1,38,0,30,x,0,0,115,1,14,14,100,x


# [bad]
# Bad channels description table
#  bad = {module_position},{apv_position},{List of 18 strip values or -1}
#
# Maps bad channels, which are then excluded from hit search. Up to 18 bad strips can be entered per line,
# more lines per APV are allowed. Unused values in the list must be filled with -1

[bad]
#bad = 2,0,73,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1

[sen]
# sensor configuration
#  sen = {sensor number},{number strips on p side},{numeration direction p},{number strips on n side},{numeration direction n},{first_full},{last_full},{pitch p [µm]}, {pitch n [µm]},{angle [°]},{height [µm]}
#  apv = {sensor number},{module_position},{apv_position},{first_strip},{num_floating},{side},0,0,0,0,0
... 193 more lines ...
Attachment 3: cern08_silc_all_multi6.cfg
# 40 mhz
# multi peak mode (6 sample)
# 50ns peaking time
# 30ns trigger window (built from 5ns window, thus ~12.5ns later)
# NECO
#
# Data processing with FADC+PROC
# SPS Testbeam - full setup
# FADC 0  four hybrids
# FADC 1  four hybrids
#
#
# CI 07 may 2008
#
#
# Lines preceded by a # or ; sign are ignored.
#
# [rem] comments a whole section until the next section start marked by [xxx] .
#

# [vme]
# VME addresses are given in the format
#  {module_name} = {vme_module_number},{vme_address_hex}
#  nec ... NECO module
#  adf ... particular FADC module
#
# Please note that the address ranges are not defined here,
# they are implicitly given by the hardware.
# Module numbers must fill from 0 (this is not checked).
# Please note that no range checking is performed.
# There is no access to VME modules that are not included in this list,

[vme]
nec = 0,0x1a000000

adf = 0,0x1b000000
adf = 1,0x2b000000

# [nec]
# NECO related information
#  mod = 0|1,{shift_register_delay},{adc_range},{win_delay},{win_length},{dead_time},{time_lat},{max_trg}
#          (default: 0,75,0,50?,900?,36,2,1)
#  res = {list of entries in reset sequence}                (default: 2,4)
#  cal = {list of entries in cal sequence}			(default: 2,3,250,251)
#  sw5 = {list of entries in single cal sequence}		(default: 2,3)
#  str = {list of entries in software trigger sequence}		(default: 75)
#  htr = {list of entries in hardware trigger sequence}		(default: 74)
#
# mod specifies to use either the sequencer (0) or the shift register (1) for hardware trigger and the
#  delay of the shift register (0..255); adc_range (0=1Vpp, 1=2Vpp) -- ignored; win_delay and win_length define
#  the starting point (relative to the APV trigger) and length of the ADC gate in transparent mode; dead_time is
#  the number of 254MHz clock cycles which are set to zero for time measurement after an incoming trigger;
#  time_lat is the latency for time measurement in terms of 40MHz clock cycles; max_trg is the number of incoming
#  triggers which required to activate the veto logic (usually 1; 0 completely disables the veto logic)
# res, cal, sw5, str and htr are containing the bits to set in the 256-element sequencer memory (nothing is set at -1)
# Please note that cal+str together produce a calibration request plus subsequent normal trigger, so the time
#  between them is the latency. sw5 is used to send a single cal request to achieve the correct polarity in
#  case the APV inverter is turned on (this feature only works for entire MAMBOs halves = groups of 3 REBOs)
# 
# These settings are quite fragile! Do not modify until you know exactly what you are doing.

[nec]

# 30m cables, 40mhz, Tp=50ns, single-trigger 
#mod = 0,75,0,70,250,36,2,1
#htr = 61,-1,-1,-1,-1,-1,-1,-1
#str = 100,-1,-1,-1,-1,-1,-1,-1

# TESTBEAM Nov 07, 30m cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 59,62,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1

# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
mod = 0,75,0,70,950,36,2,1
htr = 61,64,-1,-1,-1,-1,-1,-1
str = 100,103,-1,-1,-1,-1,-1,-1

#common settings
res =  2, 4, -1, -1,-1,-1,-1,-1
cal =  2, 3,250,251,-1,-1,-1,-1
sw5 =  2, 3, -1, -1,-1,-1,-1,-1




# [daq]
# DAQ related specifications are given in the format
#  ads = {N},{search_max_subevents},0,x
#  ini = {initevents},{readout_mode},0,x
#  deh = {module_position},{apv_position},0,x
#  i2t = {N},0,0,x
#  pat = 0,0,0,{data_file_path}
#  clk = {N},{Delay25 frequency range},0,x
#  pdl = {Trigger input delay},0,0,x
#  crd = {crate_number},{clkdel},{trgdel},x
#
# ads N gives the number of samples that are read out from the FIFO1 in transparent mode, search_max_subevents is the
#  maximum number of subevents to search for within one ADC stream (default=1).
# ini: initevents is the number of software triggers in the beginning of a run for pedestal and noise
# evaluation. At the beginning of each run, 2*initevents are generated by software, after that the 
# selected trigger source (hardware, software of calibration) is activated. The initial evaluation
# events are written to disk as normal events are.
# ini: readout_mode defines whether events beyond the initevents are read in raw transparent mode from FIFO1 (0) or
#  in processed mode (1) where only hit information is read from FIFO3
# deh is the APV chip for which single strip histograms are recorded
# i2t is the maximum number of I2C retries in case of failure
# pat specifies the save path for data files (must include a trailing backslash!)
# clk gives the system clock period in integer ns (25 max.) and the frequency range for the Delay25 chip:
#  0...40 MHz, 1...80 MHz, 2...32 MHz, 3...64 MHz
# pdl specifies the delay setting for the trigger input in 0.5ns steps (0..49)
# crd define the global clock and trigger delays between NECO and SVD3_buffer for crates 0 and 1
#  NOTE: clock and trigger is NOT propagated to any crate(s) NOT specified here


[daq]

# TESTBEAM Nov 07
#Standard
#ads = 250,1,0,x

# TESTBEAM Nov 07
#Multitrigger (6)
ads = 950,6,0,x

# RAW (transparent mode) readout
ini = 300,0,0,x

# PROCESSED readout
#ini = 300,1,0,x

deh = 1,0,0,x
i2t = 5,0,0,x
pat = 0,0,0,F:\\testbeam\\cern_jun08\\silc\\data\\

#standard 40mhz clock (25ns)
clk = 25,0,0,x
pdl = 25,0,0,x

#crate distribution delays (set to mid-range to allow adjustments in both directions)
crd = 0,25,25,x

#we don't use crate 1, so we don't set any delay here -> no clock/trigger to crate 1
###crd = 1,25,25,x


# [hit]
# Hit recognition variables are specified here
#  hcs = {hitcut_seed_strip},{hitcut_neighbor_strips}
#  nok = {x.x},0
#  
#
# hcs gives seed and neighbor hit cuts in units of strip sigma
# nok states the threshold over average noise at which strips are excluded from further analysis (to exclude noisy strips)

[hit]
# si sensor
hcs = 4.0,4.0

# do not exclude strips
nok = 2000.0,0


# [cal]
# Calibration related data
#  lvl = {level},0
#  lat = {latbeg},{latend}
#  sam = {average_samples},{number of samples in 6-tuple mode}
#  grp = {number_of_groups},0
#  lg6 = {latency},{group}
#  lv6 = {startlevel},{endlevel}
#
# lvl is the CLVL amplitude (0..255), 1 is 625e-, 36 is 1 MIP (22500e-) nominally, in reality 26 is 1 MIP
# lat is the Latency range to cover (latend-latbeg>=2, latend-latbeg<=15)
# sam is the number of samples to average per position for normal and 6-tuple modes
# grp is how many groups to scan (<=8), first group is strips 0,8,16,..., second group is 1,9,17,..., ...
# lg6 defines the latency in 6-tuple mode and which group to observe in that mode
# lv6 defines the scan range of amplitude in 6-tuple mode

[cal]
#real 1 MIP level (22400e)
lvl = 26,0

#real 5 MIPs level
#lvl = 130,0

#LAT=95/98 Calibration (short display)
#lat = 89,100

#LAT=95/98 Calibration (short display for >=50mhz)
#lat = 81,98

#LAT=95/98 Calibration (long peak mode tail display)
lat = 75,100

#common settings
sam = 50,150
grp = 8,0

#6-tuple mode settings
lg6 = 97, 1
#lv6 =  1,95
lv6 =  50,52




# [i2c]
# This section defines one or more I2C sets for the APV25. In the [mod] section, those sets are referenced to by their number.
#  ia2 = {number},{mode},{lat},{ipre},{ipcasc},{ipsf},{isha},{issf},{ipsp},{imuxin},{vfp},{vfs},{vpsp},{muxgain}
#
# The I2C settings must be individually numbered (ascending from 0). The easiest case is to use the same
# settings for all chips of one type, but one could go so far to use separate settings for each chip.
# vadj/vpsp is set individually for each apv in the [mod] section, the value specified here is meaningless.

[i2c]

# apv25s1, peak, inverter ON, Tp=50ns, (p side)
#ia2 =          0,    63,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, peak, inverter OFF, Tp=50ns, (n side)
#ia2 =          1,    31,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# apv25s1, multi-peak, inverter ON, Tp=50ns, (p side)
ia2 =          0,    61,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side)
ia2 =          1,    29,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# [mod]
# Detector module (actually hybrid) specifications are given in the format
#  mod = {module_position},{crate_number},{mambo_number},{rebo_number},{hybrid_number},m,{AD8128_peak},{rebo_clkdelay},{rebo_trgdelay},0,0,0,0,{Name}
#  apv = {module_position},{apv_position},{i2c_address},{i2c_settings},{vadj/vpsp},x,0,0,{fadc_offset},{fadc_number},{fadc_channel},{fadc_clkdelay [0..49]},{AD8128_gain},x
#
# mod gives the hybrid/module properties: The position counts from 0 to 7 in beam direction,
#  Name must not contain blanks ("_" is allowed).
# apv describes the chips located on a hybrid 
#  and the ADC channel where they are read out, either a Vienna ADC (a) or a FED (f).
# The ADC offset is only available with the Vienna ADCs and shifts the baseline.
# The individual chip vadj setting dominates over the [i2c] setting.


[mod]

# module 0
mod = 0,0,0,2,0,m,45,25,0,0,0,0,0, 0_SiLC_05/05
apv = 0,0,36,0,30,x,0,0,5,0,1,12,100,x
apv = 0,1,38,0,30,x,0,0,5,0,2,15,100,x
# module 1
mod = 1,0,0,2,1,m,45,25,0,0,0,0,0, 1_SiLC_07/07
apv = 1,0,36,0,30,x,0,0,5,0,5,15,100,x
apv = 1,1,38,0,30,x,0,0,5,0,6,16,100,x
# module 2
mod = 2,0,0,2,2,m,45,25,0,0,0,0,0, 2_SiLC_06/03
apv = 2,0,36,0,30,x,0,0,5,0,9,10,100,x
apv = 2,1,38,0,30,x,0,0,5,0,10,15,100,x
# module 3
mod = 3,0,0,2,3,m,45,25,0,0,0,0,0, 3_SiLC_04/04
apv = 3,0,36,0,30,x,0,0,5,0,13,12,100,x
apv = 3,1,38,0,30,x,0,0,5,0,14,14,100,x
# module 4
mod = 4,0,1,1,0,m,45,25,0,0,0,0,0, 4_SiLC_03/10
apv = 4,0,36,0,30,x,0,0,110,1,1,14,100,x
apv = 4,1,38,0,30,x,0,0,110,1,2,15,100,x
# module 5
mod = 5,0,1,1,1,m,45,25,0,0,0,0,0, 5_SiLC_12/08
apv = 5,0,36,0,30,x,0,0,110,1,5,14,100,x
apv = 5,1,38,0,30,x,0,0,110,1,6,16,100,x
# module 6
mod = 6,0,1,1,2,m,45,25,0,0,0,0,0, 6_SiLC_10/02
apv = 6,0,36,0,30,x,0,0,110,1,9,12,100,x
apv = 6,1,38,0,30,x,0,0,120,1,10,15,100,x
# module 7
mod = 7,0,1,1,3,m,45,25,0,0,0,0,0, 7_SiLC_20/09
apv = 7,0,36,0,30,x,0,0,125,1,13,10,100,x
apv = 7,1,38,0,30,x,0,0,115,1,14,14,100,x


# [bad]
# Bad channels description table
#  bad = {module_position},{apv_position},{List of 18 strip values or -1}
#
# Maps bad channels, which are then excluded from hit search. Up to 18 bad strips can be entered per line,
# more lines per APV are allowed. Unused values in the list must be filled with -1

[bad]
#bad = 2,0,73,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1

[sen]
# sensor configuration
#  sen = {sensor number},{number strips on p side},{numeration direction p},{number strips on n side},{numeration direction n},{first_full},{last_full},{pitch p [µm]}, {pitch n [µm]},{angle [°]},{height [µm]}
#  apv = {sensor number},{module_position},{apv_position},{first_strip},{num_floating},{side},0,0,0,0,0
#  zon = {sensor number},{zone number},{first strip on p side},{last strip on p side},{first strip on n side},{last strip on n side},0,0,0,0,0
#
# sen defines the sensor proberties:
#  numeration direction can be 0 = from left to right or 1 = from right to left
#	
# apv describes the apvs connected to the sensor
... 187 more lines ...
Attachment 4: cern08_silc_mod03_single.cfg
# 40 mhz
# single peak mode (1 sample)
# 50ns peaking time
# 30ns trigger window (built from 5ns window, thus ~12.5ns later)
# NECO
#
# Data processing with FADC+PROC
# SPS Testbeam - single module
# FADC 0  one module at position 3
# FADC 1  not used
#
#
# CI 07 may 2008
#
#
# Lines preceded by a # or ; sign are ignored.
#
# [rem] comments a whole section until the next section start marked by [xxx] .
#

# [vme]
# VME addresses are given in the format
#  {module_name} = {vme_module_number},{vme_address_hex}
#  nec ... NECO module
#  adf ... particular FADC module
#
# Please note that the address ranges are not defined here,
# they are implicitly given by the hardware.
# Module numbers must fill from 0 (this is not checked).
# Please note that no range checking is performed.
# There is no access to VME modules that are not included in this list,

[vme]
nec = 0,0x1a000000

adf = 0,0x1b000000
#adf = 1,0x2b000000

# [nec]
# NECO related information
#  mod = 0|1,{shift_register_delay},{adc_range},{win_delay},{win_length},{dead_time},{time_lat},{max_trg}
#          (default: 0,75,0,50?,900?,36,2,1)
#  res = {list of entries in reset sequence}                (default: 2,4)
#  cal = {list of entries in cal sequence}			(default: 2,3,250,251)
#  sw5 = {list of entries in single cal sequence}		(default: 2,3)
#  str = {list of entries in software trigger sequence}		(default: 75)
#  htr = {list of entries in hardware trigger sequence}		(default: 74)
#
# mod specifies to use either the sequencer (0) or the shift register (1) for hardware trigger and the
#  delay of the shift register (0..255); adc_range (0=1Vpp, 1=2Vpp) -- ignored; win_delay and win_length define
#  the starting point (relative to the APV trigger) and length of the ADC gate in transparent mode; dead_time is
#  the number of 254MHz clock cycles which are set to zero for time measurement after an incoming trigger;
#  time_lat is the latency for time measurement in terms of 40MHz clock cycles; max_trg is the number of incoming
#  triggers which required to activate the veto logic (usually 1; 0 completely disables the veto logic)
# res, cal, sw5, str and htr are containing the bits to set in the 256-element sequencer memory (nothing is set at -1)
# Please note that cal+str together produce a calibration request plus subsequent normal trigger, so the time
#  between them is the latency. sw5 is used to send a single cal request to achieve the correct polarity in
#  case the APV inverter is turned on (this feature only works for entire MAMBOs halves = groups of 3 REBOs)
# 
# These settings are quite fragile! Do not modify until you know exactly what you are doing.

[nec]

# 30m cables, 40mhz, Tp=50ns, single-trigger 
#mod = 0,75,0,70,250,36,2,1
#htr = 61,-1,-1,-1,-1,-1,-1,-1
#str = 100,-1,-1,-1,-1,-1,-1,-1

# TESTBEAM Nov 07, 30m cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 59,62,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1

# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, single-trigger (1 samples)
mod = 0,75,0,70,250,36,2,1
htr = 63,-1,-1,-1,-1,-1,-1,-1
str = 100,-1,-1,-1,-1,-1,-1,-1

# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 61,64,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1


#common settings
res =  2, 4, -1, -1,-1,-1,-1,-1
cal =  2, 3,250,251,-1,-1,-1,-1
sw5 =  2, 3, -1, -1,-1,-1,-1,-1




# [daq]
# DAQ related specifications are given in the format
#  ads = {N},{search_max_subevents},0,x
#  ini = {initevents},{readout_mode},0,x
#  deh = {module_position},{apv_position},0,x
#  i2t = {N},0,0,x
#  pat = 0,0,0,{data_file_path}
#  clk = {N},{Delay25 frequency range},0,x
#  pdl = {Trigger input delay},0,0,x
#  crd = {crate_number},{clkdel},{trgdel},x
#
# ads N gives the number of samples that are read out from the FIFO1 in transparent mode, search_max_subevents is the
#  maximum number of subevents to search for within one ADC stream (default=1).
# ini: initevents is the number of software triggers in the beginning of a run for pedestal and noise
# evaluation. At the beginning of each run, 2*initevents are generated by software, after that the 
# selected trigger source (hardware, software of calibration) is activated. The initial evaluation
# events are written to disk as normal events are.
# ini: readout_mode defines whether events beyond the initevents are read in raw transparent mode from FIFO1 (0) or
#  in processed mode (1) where only hit information is read from FIFO3
# deh is the APV chip for which single strip histograms are recorded
# i2t is the maximum number of I2C retries in case of failure
# pat specifies the save path for data files (must include a trailing backslash!)
# clk gives the system clock period in integer ns (25 max.) and the frequency range for the Delay25 chip:
#  0...40 MHz, 1...80 MHz, 2...32 MHz, 3...64 MHz
# pdl specifies the delay setting for the trigger input in 0.5ns steps (0..49)
# crd define the global clock and trigger delays between NECO and SVD3_buffer for crates 0 and 1
#  NOTE: clock and trigger is NOT propagated to any crate(s) NOT specified here


[daq]

# TESTBEAM Nov 07
#Standard
ads = 250,1,0,x

# TESTBEAM Nov 07
#Multitrigger (6)
#ads = 950,6,0,x

# RAW (transparent mode) readout
ini = 300,0,0,x

# PROCESSED readout
#ini = 300,1,0,x

deh = 1,0,0,x
i2t = 5,0,0,x
pat = 0,0,0,F:\\testbeam\\cern_jun08\\silc\\data\\

#standard 40mhz clock (25ns)
clk = 25,0,0,x
pdl = 25,0,0,x

#crate distribution delays (set to mid-range to allow adjustments in both directions)
crd = 0,25,25,x

#we don't use crate 1, so we don't set any delay here -> no clock/trigger to crate 1
###crd = 1,25,25,x


# [hit]
# Hit recognition variables are specified here
#  hcs = {hitcut_seed_strip},{hitcut_neighbor_strips}
#  nok = {x.x},0
#  
#
# hcs gives seed and neighbor hit cuts in units of strip sigma
# nok states the threshold over average noise at which strips are excluded from further analysis (to exclude noisy strips)

[hit]
# si sensor
hcs = 4.0,4.0

# do not exclude strips
nok = 2000.0,0


# [cal]
# Calibration related data
#  lvl = {level},0
#  lat = {latbeg},{latend}
#  sam = {average_samples},{number of samples in 6-tuple mode}
#  grp = {number_of_groups},0
#  lg6 = {latency},{group}
#  lv6 = {startlevel},{endlevel}
#
# lvl is the CLVL amplitude (0..255), 1 is 625e-, 36 is 1 MIP (22500e-) nominally, in reality 26 is 1 MIP
# lat is the Latency range to cover (latend-latbeg>=2, latend-latbeg<=15)
# sam is the number of samples to average per position for normal and 6-tuple modes
# grp is how many groups to scan (<=8), first group is strips 0,8,16,..., second group is 1,9,17,..., ...
# lg6 defines the latency in 6-tuple mode and which group to observe in that mode
# lv6 defines the scan range of amplitude in 6-tuple mode

[cal]
#real 1 MIP level (22400e)
lvl = 26,0

#real 5 MIPs level
#lvl = 130,0

#LAT=95/98 Calibration (short display)
#lat = 89,100

#LAT=95/98 Calibration (short display for >=50mhz)
#lat = 81,98

#LAT=95/98 Calibration (long peak mode tail display)
lat = 75,100

#common settings
sam = 50,150
grp = 8,0

#6-tuple mode settings
lg6 = 97, 1
#lv6 =  1,95
lv6 =  50,52




# [i2c]
# This section defines one or more I2C sets for the APV25. In the [mod] section, those sets are referenced to by their number.
#  ia2 = {number},{mode},{lat},{ipre},{ipcasc},{ipsf},{isha},{issf},{ipsp},{imuxin},{vfp},{vfs},{vpsp},{muxgain}
#
# The I2C settings must be individually numbered (ascending from 0). The easiest case is to use the same
# settings for all chips of one type, but one could go so far to use separate settings for each chip.
# vadj/vpsp is set individually for each apv in the [mod] section, the value specified here is meaningless.

[i2c]

# apv25s1, peak, inverter ON, Tp=50ns, (p side)
ia2 =          0,    63,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, peak, inverter OFF, Tp=50ns, (n side)
ia2 =          1,    31,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# apv25s1, multi-peak, inverter ON, Tp=50ns, (p side)
#ia2 =          0,    61,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side)
#ia2 =          1,    29,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# [mod]
# Detector module (actually hybrid) specifications are given in the format
#  mod = {module_position},{crate_number},{mambo_number},{rebo_number},{hybrid_number},m,{AD8128_peak},{rebo_clkdelay},{rebo_trgdelay},0,0,0,0,{Name}
#  apv = {module_position},{apv_position},{i2c_address},{i2c_settings},{vadj/vpsp},x,0,0,{fadc_offset},{fadc_number},{fadc_channel},{fadc_clkdelay [0..49]},{AD8128_gain},x
#
# mod gives the hybrid/module properties: The position counts from 0 to 7 in beam direction,
#  Name must not contain blanks ("_" is allowed).
# apv describes the chips located on a hybrid 
#  and the ADC channel where they are read out, either a Vienna ADC (a) or a FED (f).
# The ADC offset is only available with the Vienna ADCs and shifts the baseline.
# The individual chip vadj setting dominates over the [i2c] setting.


[mod]

# module 3
mod = 3,0,0,2,3,m,45,25,0,0,0,0,0, 3_SiLC_04/04
apv = 3,0,36,0,30,x,0,0,5,0,13,12,100,x
apv = 3,1,38,0,30,x,0,0,5,0,14,14,100,x


# [bad]
# Bad channels description table
#  bad = {module_position},{apv_position},{List of 18 strip values or -1}
#
# Maps bad channels, which are then excluded from hit search. Up to 18 bad strips can be entered per line,
# more lines per APV are allowed. Unused values in the list must be filled with -1

[bad]
#bad = 2,0,73,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1

[sen]
# sensor configuration
#  sen = {sensor number},{number strips on p side},{numeration direction p},{number strips on n side},{numeration direction n},{first_full},{last_full},{pitch p [µm]}, {pitch n [µm]},{angle [°]},{height [µm]}
#  apv = {sensor number},{module_position},{apv_position},{first_strip},{num_floating},{side},0,0,0,0,0
#  zon = {sensor number},{zone number},{first strip on p side},{last strip on p side},{first strip on n side},{last strip on n side},0,0,0,0,0
#
# sen defines the sensor proberties:
#  numeration direction can be 0 = from left to right or 1 = from right to left
#	
# apv describes the apvs connected to the sensor
#  module_position and apv_position must be identical to the values in section [mod]
#  first_strip is the strip number bonded to channel 0
#  num_floating is the number of floating strips between two apv channels, set it to 0 if all strips are bonded.
#  side: 0 = the apv is bonded to the n side of the sensor
#        1 = the apv is bonded to the p side of the sensor
#
# zon defines zones of strips with similar properties, e.g.bonding density
#  for each zone the data should be processed separately
#  zone number: this is the number of the zone on one sensor


# module 3
sen = 1,256,0,256,0,0,256,50.0,50.0,90,12750.0 
apv = 1,3,0,0,0,1,0,0,0,0,0
apv = 1,3,1,128,0,1,0,0,0,0,0

zon = 1,1,0,15,0,0,0,0,0,0,0
zon = 1,2,16,31,0,0,0,0,0,0,0
zon = 1,3,32,47,0,0,0,0,0,0,0
zon = 1,4,48,63,0,0,0,0,0,0,0
zon = 1,5,64,79,0,0,0,0,0,0,0
zon = 1,6,80,95,0,0,0,0,0,0,0
... 11 more lines ...
Attachment 5: cern08_silc_mod03_multi6.cfg
# 40 mhz
# multi peak mode (6 sample)
# 50ns peaking time
# 30ns trigger window (built from 5ns window, thus ~12.5ns later)
# NECO
#
# Data processing with FADC+PROC
# SPS Testbeam - single module
# FADC 0  one module at position 3
# FADC 1  not used
#
#
# CI 07 may 2008
#
#
# Lines preceded by a # or ; sign are ignored.
#
# [rem] comments a whole section until the next section start marked by [xxx] .
#

# [vme]
# VME addresses are given in the format
#  {module_name} = {vme_module_number},{vme_address_hex}
#  nec ... NECO module
#  adf ... particular FADC module
#
# Please note that the address ranges are not defined here,
# they are implicitly given by the hardware.
# Module numbers must fill from 0 (this is not checked).
# Please note that no range checking is performed.
# There is no access to VME modules that are not included in this list,

[vme]
nec = 0,0x1a000000

adf = 0,0x1b000000
#adf = 1,0x2b000000

# [nec]
# NECO related information
#  mod = 0|1,{shift_register_delay},{adc_range},{win_delay},{win_length},{dead_time},{time_lat},{max_trg}
#          (default: 0,75,0,50?,900?,36,2,1)
#  res = {list of entries in reset sequence}                (default: 2,4)
#  cal = {list of entries in cal sequence}			(default: 2,3,250,251)
#  sw5 = {list of entries in single cal sequence}		(default: 2,3)
#  str = {list of entries in software trigger sequence}		(default: 75)
#  htr = {list of entries in hardware trigger sequence}		(default: 74)
#
# mod specifies to use either the sequencer (0) or the shift register (1) for hardware trigger and the
#  delay of the shift register (0..255); adc_range (0=1Vpp, 1=2Vpp) -- ignored; win_delay and win_length define
#  the starting point (relative to the APV trigger) and length of the ADC gate in transparent mode; dead_time is
#  the number of 254MHz clock cycles which are set to zero for time measurement after an incoming trigger;
#  time_lat is the latency for time measurement in terms of 40MHz clock cycles; max_trg is the number of incoming
#  triggers which required to activate the veto logic (usually 1; 0 completely disables the veto logic)
# res, cal, sw5, str and htr are containing the bits to set in the 256-element sequencer memory (nothing is set at -1)
# Please note that cal+str together produce a calibration request plus subsequent normal trigger, so the time
#  between them is the latency. sw5 is used to send a single cal request to achieve the correct polarity in
#  case the APV inverter is turned on (this feature only works for entire MAMBOs halves = groups of 3 REBOs)
# 
# These settings are quite fragile! Do not modify until you know exactly what you are doing.

[nec]

# 30m cables, 40mhz, Tp=50ns, single-trigger 
#mod = 0,75,0,70,250,36,2,1
#htr = 61,-1,-1,-1,-1,-1,-1,-1
#str = 100,-1,-1,-1,-1,-1,-1,-1

# TESTBEAM Nov 07, 30m cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 59,62,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1

# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
mod = 0,75,0,70,950,36,2,1
htr = 61,64,-1,-1,-1,-1,-1,-1
str = 100,103,-1,-1,-1,-1,-1,-1

#common settings
res =  2, 4, -1, -1,-1,-1,-1,-1
cal =  2, 3,250,251,-1,-1,-1,-1
sw5 =  2, 3, -1, -1,-1,-1,-1,-1




# [daq]
# DAQ related specifications are given in the format
#  ads = {N},{search_max_subevents},0,x
#  ini = {initevents},{readout_mode},0,x
#  deh = {module_position},{apv_position},0,x
#  i2t = {N},0,0,x
#  pat = 0,0,0,{data_file_path}
#  clk = {N},{Delay25 frequency range},0,x
#  pdl = {Trigger input delay},0,0,x
#  crd = {crate_number},{clkdel},{trgdel},x
#
# ads N gives the number of samples that are read out from the FIFO1 in transparent mode, search_max_subevents is the
#  maximum number of subevents to search for within one ADC stream (default=1).
# ini: initevents is the number of software triggers in the beginning of a run for pedestal and noise
# evaluation. At the beginning of each run, 2*initevents are generated by software, after that the 
# selected trigger source (hardware, software of calibration) is activated. The initial evaluation
# events are written to disk as normal events are.
# ini: readout_mode defines whether events beyond the initevents are read in raw transparent mode from FIFO1 (0) or
#  in processed mode (1) where only hit information is read from FIFO3
# deh is the APV chip for which single strip histograms are recorded
# i2t is the maximum number of I2C retries in case of failure
# pat specifies the save path for data files (must include a trailing backslash!)
# clk gives the system clock period in integer ns (25 max.) and the frequency range for the Delay25 chip:
#  0...40 MHz, 1...80 MHz, 2...32 MHz, 3...64 MHz
# pdl specifies the delay setting for the trigger input in 0.5ns steps (0..49)
# crd define the global clock and trigger delays between NECO and SVD3_buffer for crates 0 and 1
#  NOTE: clock and trigger is NOT propagated to any crate(s) NOT specified here


[daq]

# TESTBEAM Nov 07
#Standard
#ads = 250,1,0,x

# TESTBEAM Nov 07
#Multitrigger (6)
ads = 950,6,0,x

# RAW (transparent mode) readout
ini = 300,0,0,x

# PROCESSED readout
#ini = 300,1,0,x

deh = 1,0,0,x
i2t = 5,0,0,x
pat = 0,0,0,F:\\testbeam\\cern_jun08\\silc\\data\\

#standard 40mhz clock (25ns)
clk = 25,0,0,x
pdl = 25,0,0,x

#crate distribution delays (set to mid-range to allow adjustments in both directions)
crd = 0,25,25,x

#we don't use crate 1, so we don't set any delay here -> no clock/trigger to crate 1
###crd = 1,25,25,x


# [hit]
# Hit recognition variables are specified here
#  hcs = {hitcut_seed_strip},{hitcut_neighbor_strips}
#  nok = {x.x},0
#  
#
# hcs gives seed and neighbor hit cuts in units of strip sigma
# nok states the threshold over average noise at which strips are excluded from further analysis (to exclude noisy strips)

[hit]
# si sensor
hcs = 4.0,4.0

# do not exclude strips
nok = 2000.0,0


# [cal]
# Calibration related data
#  lvl = {level},0
#  lat = {latbeg},{latend}
#  sam = {average_samples},{number of samples in 6-tuple mode}
#  grp = {number_of_groups},0
#  lg6 = {latency},{group}
#  lv6 = {startlevel},{endlevel}
#
# lvl is the CLVL amplitude (0..255), 1 is 625e-, 36 is 1 MIP (22500e-) nominally, in reality 26 is 1 MIP
# lat is the Latency range to cover (latend-latbeg>=2, latend-latbeg<=15)
# sam is the number of samples to average per position for normal and 6-tuple modes
# grp is how many groups to scan (<=8), first group is strips 0,8,16,..., second group is 1,9,17,..., ...
# lg6 defines the latency in 6-tuple mode and which group to observe in that mode
# lv6 defines the scan range of amplitude in 6-tuple mode

[cal]
#real 1 MIP level (22400e)
lvl = 26,0

#real 5 MIPs level
#lvl = 130,0

#LAT=95/98 Calibration (short display)
#lat = 89,100

#LAT=95/98 Calibration (short display for >=50mhz)
#lat = 81,98

#LAT=95/98 Calibration (long peak mode tail display)
lat = 75,100

#common settings
sam = 50,150
grp = 8,0

#6-tuple mode settings
lg6 = 97, 1
#lv6 =  1,95
lv6 =  50,52




# [i2c]
# This section defines one or more I2C sets for the APV25. In the [mod] section, those sets are referenced to by their number.
#  ia2 = {number},{mode},{lat},{ipre},{ipcasc},{ipsf},{isha},{issf},{ipsp},{imuxin},{vfp},{vfs},{vpsp},{muxgain}
#
# The I2C settings must be individually numbered (ascending from 0). The easiest case is to use the same
# settings for all chips of one type, but one could go so far to use separate settings for each chip.
# vadj/vpsp is set individually for each apv in the [mod] section, the value specified here is meaningless.

[i2c]

# apv25s1, peak, inverter ON, Tp=50ns, (p side)
#ia2 =          0,    63,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, peak, inverter OFF, Tp=50ns, (n side)
#ia2 =          1,    31,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# apv25s1, multi-peak, inverter ON, Tp=50ns, (p side)
ia2 =          0,    61,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4

# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side)
ia2 =          1,    29,   95,    98,      52,    34,    34,    34,    55,      34,   30,   60,     0,       4


# [mod]
# Detector module (actually hybrid) specifications are given in the format
#  mod = {module_position},{crate_number},{mambo_number},{rebo_number},{hybrid_number},m,{AD8128_peak},{rebo_clkdelay},{rebo_trgdelay},0,0,0,0,{Name}
#  apv = {module_position},{apv_position},{i2c_address},{i2c_settings},{vadj/vpsp},x,0,0,{fadc_offset},{fadc_number},{fadc_channel},{fadc_clkdelay [0..49]},{AD8128_gain},x
#
# mod gives the hybrid/module properties: The position counts from 0 to 7 in beam direction,
#  Name must not contain blanks ("_" is allowed).
# apv describes the chips located on a hybrid 
#  and the ADC channel where they are read out, either a Vienna ADC (a) or a FED (f).
# The ADC offset is only available with the Vienna ADCs and shifts the baseline.
# The individual chip vadj setting dominates over the [i2c] setting.


[mod]

# module 3
mod = 3,0,0,2,3,m,45,25,0,0,0,0,0, 3_SiLC_04/04
apv = 3,0,36,0,30,x,0,0,5,0,13,12,100,x
apv = 3,1,38,0,30,x,0,0,5,0,14,14,100,x


# [bad]
# Bad channels description table
#  bad = {module_position},{apv_position},{List of 18 strip values or -1}
#
# Maps bad channels, which are then excluded from hit search. Up to 18 bad strips can be entered per line,
# more lines per APV are allowed. Unused values in the list must be filled with -1

[bad]
#bad = 2,0,73,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1

[sen]
# sensor configuration
#  sen = {sensor number},{number strips on p side},{numeration direction p},{number strips on n side},{numeration direction n},{first_full},{last_full},{pitch p [µm]}, {pitch n [µm]},{angle [°]},{height [µm]}
#  apv = {sensor number},{module_position},{apv_position},{first_strip},{num_floating},{side},0,0,0,0,0
#  zon = {sensor number},{zone number},{first strip on p side},{last strip on p side},{first strip on n side},{last strip on n side},0,0,0,0,0
#
# sen defines the sensor proberties:
#  numeration direction can be 0 = from left to right or 1 = from right to left
#	
# apv describes the apvs connected to the sensor
#  module_position and apv_position must be identical to the values in section [mod]
#  first_strip is the strip number bonded to channel 0
#  num_floating is the number of floating strips between two apv channels, set it to 0 if all strips are bonded.
#  side: 0 = the apv is bonded to the n side of the sensor
#        1 = the apv is bonded to the p side of the sensor
#
# zon defines zones of strips with similar properties, e.g.bonding density
#  for each zone the data should be processed separately
#  zone number: this is the number of the zone on one sensor

# module 3
sen = 1,256,0,256,0,0,256,50.0,50.0,90,12750.0 
apv = 1,3,0,0,0,1,0,0,0,0,0
apv = 1,3,1,128,0,1,0,0,0,0,0

zon = 1,1,0,15,0,0,0,0,0,0,0
zon = 1,2,16,31,0,0,0,0,0,0,0
zon = 1,3,32,47,0,0,0,0,0,0,0
zon = 1,4,48,63,0,0,0,0,0,0,0
zon = 1,5,64,79,0,0,0,0,0,0,0
zon = 1,6,80,95,0,0,0,0,0,0,0
zon = 1,7,96,111,0,0,0,0,0,0,0
zon = 1,8,112,127,0,0,0,0,0,0,0
zon = 1,9,128,143,0,0,0,0,0,0,0
zon = 1,10,144,159,0,0,0,0,0,0,0
zon = 1,11,160,175,0,0,0,0,0,0,0
zon = 1,12,176,191,0,0,0,0,0,0,0
zon = 1,13,192,207,0,0,0,0,0,0,0
... 5 more lines ...
  10   Fri May 23 15:17:49 2008 Markus FriedlSiLCModule/chip/strip/zone numbering scheme(work in progress)   
The SILC DUT is a stack of 8 silicon sensors surrounded by the telescope.
The spacing between each of the 8 layers is 20mm. Seen with the beam, the fourth layer is exactly centered
between the telescope legs. This means that the stack as a whole is not exactly centered, as there is no
'center' module with an even number of layers. Please refer to drawings "telecope_single_dut.gif" and
"telescope_8_dut.gif" below.

Each sensor has 256 strips, which are read out by 2 APV25 chips. The numbering order of the modules follows the
beam direction (see drawing "silc_dut_stack_beam.jpg"). Modules will have the connector (and thus APV25 hybrid)
at the top as shown in the photos. The numbering scheme within one module is shown in drawing
"silc_dut_beam.jpg": Looking with the beam, strips are numbered from right to left. The strip pitch is 50um
everywhere.

The APVDAQ software works on APV25 level for the data acquisition, where raw data is saved. In that case, the
APVs are consecutively numbered 0,1 (=module 0), 2,3 (=module 1), 4,5 (=module 2), ... ,14,15 (=module 7).
In later steps of the analysis, data are presented on a module [0..7] / strip [0..511] base.
Zone numbers were removed, now everything is zone=1.
(Zone 0 is a reserved value and hence the actual zone counting starts with 1.)

The 256 strips are divided into 16 groups of 16 strips each with different strip width and intermediate strips,
according to the table below:
	 	pplus strip  	number of
		width 	intermediate
group#	strips 	[µm] 	strips
 0	16 	6 	none
 1	16 	10 	none
 2	16 	12.5 	none
 3	16 	15 	none
 4	16 	20 	none
 5	16 	25 	none
 6	16 	6 	single
 7	16 	7.5 	single
 8	16 	10 	single
 9	16 	12.5 	single
10	16 	15 	single
11	16 	17.5 	single
12	16 	6 	double
13	16 	7.5 	double
14	16 	10 	double
15	16 	12.5 	double

Please note that the strip pitch is 50µm everywhere, but between each group there is a gap of a single missing
strip. Hence, when calculating the coordinate from the strip number, one must take those distinctive gaps into
account.

We assume that we have a fractional strip position, where the fraction denotes (e.g.) the center of gravity of
the cluster. In order to convert this into a coordinate, we can use the following approach (where s is the
(fractional) strip number and x ist the fractional coordinate [µm]):

 /* *** tested and works *** */

double strip2x(double strip)
{
 unsigned short ints;

 // this is the integral part of the strip number
 ints = (unsigned short) strip;
 
 return ( 50.0 * ( strip + ( ints >> 4 ) ) + ( ( (ints+1) & 15 ) ? 0.0 : ( strip - ints ) * 50.0 ) );
 //       pitch    strip 
 //                          gaps between zones
 //                                                outside gap ? do nothing
 //                                                                      account for double pitch within gap 
    
}
Attachment 1: telescope_single_dut.gif
telescope_single_dut.gif
Attachment 2: telescope_8_dut.gif
telescope_8_dut.gif
Attachment 3: silc_dut_stack_beam.jpg
silc_dut_stack_beam.jpg
Attachment 4: silc_dut_beam.jpg
silc_dut_beam.jpg
  9   Mon May 19 15:21:49 2008 Markus FriedlotherCERN SPS page 1    

SPS Status

SPS Page 1 - http://hpslweb.cern.ch/frame/java/1.1/view110-java.html

Manual - http://jwenning.web.cern.ch/jwenning/documents/SPS/Operation/Page-1%20description.htm

Linac, PSB, CPS Status

Linac, PSB, CPS Status
  8   Mon May 19 15:14:40 2008 Markus FriedlotherTentative Beam Test Schedule    
Wed 28 May: ~16:00 arrival, unpacking
Thu 29 May: installation
Fri 30 May: beam on

1) Telescope + 8xSilC (~7hrs, overnight; first part)
2) 8xSilc, no telescope (fast runs during day)
3) Telescope + 8xSilC (~7hrs, overnight; second part after DUT shift)
4) 1xSilc, rotation
5) Belle, telescope

* starting telescope alignement
* adc delay scan, intcal, pedrun, pedcorr
* DUT alignement
* std. settings, telescope zero supr.(zp) 1st half, lunch break
* std. settings, telescope zero supr. 2nd half
* std. settings, telescope raw data, 1st half
* std. settings, telescope raw data, 2nd half
* optionally HV scan, tel. zp., (10 HV settings --> 2x 10 runs)
* unmount 7 DUTs
* std run 0 deg., (2 runs)
* angle scan (about 10 runs)      
* install Belle DUT
* std. settings, telescope raw, transparent mode
* std. settings, telescope sp, transparent mode, high statistics
* std. settings, telescope sp, processed mode, high statistics
  7   Wed May 14 16:15:30 2008 Markus FriedlBELLEMicron DDD5 Photos    
This is the new Micron DDD5 double-sided module with 3+3 APV25 readout chips on each side.

The p-side flex hybrid sits at the edge of the sensor, while the n-side flex hybrid is located on top of about
1/3 of the sensor, separated by 1mm of Rohacell.

Sensor data (copied from the Micron catalogue):

DESIGN DDD5 - AC COUPLED ION IMPLANTED TOTALLY DEPLETED DOUBLE SIDED DOUBLE METAL MICROSTRIP DETECTOR

SILICON DETECTOR TYPE: AC coupled ion implanted totally depleted silicon microstrip detector.
DESIGN: Double sided, two metal layers on NN+ 6 inch wafer technology.

JUNCTION SIDE
No STRIPS: 384
STRIP PITCH: 50 µm

OHMIC SIDE
First Metal
No STRIPS: 768
STRIP PITCH: 153.5 µm
Second Metal
No STRIPS: 384
STRIP PITCH: 49.5 µm

POLYSILICON RESISTOR: 2.5 ± 0.5 M
COUPLING CAPACITOR: 100 pF
SILICON THICKNESS: 300 ± 10 µm
CHIP DIMENSIONS: 120.125 x 21.2 mm2
FULL DEPLETION VOLTAGE (FD): 50 V maximum
OPERATING VOLTAGE: FD to 2FD

EXPERIMENTS: D2, FNAL
Attachment 1: micron_pside.jpg
micron_pside.jpg
Attachment 2: micron_nside.jpg
micron_nside.jpg
Attachment 3: micron_pside_detail.jpg
micron_pside_detail.jpg
Attachment 4: micron_nside_detail.jpg
micron_nside_detail.jpg
  6   Wed May 14 09:21:39 2008 stephan hänselSiLCcapacity measurements - HPK-ILC-TS-6687-24    
ich hab mal die Kapazitäts-Messungen vom Thomas in ein Diagram gegeben

interessant ist, dass die Kapazität mit 2 intermediate strips (int. strips) kleiner ist als mit einem int. strip -> das bedeutet, dass der eine int. strip breiter ist als die 2 int. strips zusammen - oder?
weiters dürfte die breite des einen int. strips mit der stripwith leicht variieren

(zur Erinnerung: Plattenkondensator - C = e eo A / d )
Attachment 1: capacity-TS24.eps
Attachment 2: capacity_measurements_ACTS-24.opj
ELOG V3.1.5-fc6679b