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  Belle testbeam at SPS in June 2015, Page 5 of 6  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
Entry  Sun Jun 7 10:36:38 2015, Hao Yin, Belle II FADC (H6A), Pedestal, 006, 10000, , , Unknown Pos1.PNG

Cooled, Temp see attachment
FirRun002
 

Entry  Sun Jun 7 00:58:33 2015, Benedikt Würkner, SVD3 (H6B), hardware run, hw006, , , , Crap 

Table: 100:70

Bias: +-50V

600 pedestal

0 offset (at the beginning)

Started APVDAQ and waited till 600 were taken then started EUDAQ

EUDAQ Run 24

Mimosa Thresholds lvl 7

Entry  Sat Jun 6 23:30:29 2015, Benedikt Würkner, Belle II FADC (H6A), Hardware, 009, , , , Good 

room temp, FIRRun002, PedestalRun005, room temp

target: FW, pos 9 (p-0, n-128*4)

Entry  Sat Jun 6 21:00:15 2015, Benedikt Würkner, SVD3 (H6B), first hardware run with TLU and Telescope, hw004, 117171, , , Unknown 

Table: 100:70

Bias: +-50V

600 pedestal

0 offset (at the beginning)

Started APVDAQ and waited till 600 were taken then started EUDAQ

EUDAQ Run 21

Mimosa Thresholds lvl 6

Entry  Sat Jun 6 16:48:41 2015, Hao Yin, Belle II FADC (H6A), Hardware, 008, 50000, 8, No, Good 20x

room temp, FIRRun002, PedestalRun005, room temp

target: FW, pos 8 (p-0, n-0)

Entry  Sat Jun 6 16:18:48 2015, Benedikt Würkner, SVD3 (H6B), hardware run, hw003, 50000, , , Unknown 

Table: 100:70

Bias: +-50V

Run to confirm trigger delay

Entry  Sat Jun 6 16:17:52 2015, Benedikt Würkner, SVD3 (H6B), hardware run, hw002, 5000, , , Good 

Table: 100:70

Bias: +-50V

Run to confirm trigger delay

Entry  Sat Jun 6 16:14:36 2015, Benedikt Würkner, SVD3 (H6B), calibration run and setup information, cal01, , , , Unknown 

Calibration Run with +- 50V Bias with higher compliance since the p-side draws more current than expected (23muA by the MAMBO)

 

Entry  Sat Jun 6 14:28:28 2015, Hao Yin, Belle II FADC (H6A), Harware, 007, 50000, 7, No, Good 20x

room temp, FIRRun002, PedestalRun005, room temp

target: CE, pos 7 (p-0, n-0)

Entry  Sat Jun 6 12:43:55 2015, Hao Yin, Belle II FADC (H6A), Hardware, 006, 50000, 6, No, Good 20x

FIRRun002, room temp, pedestalrun005,
layout: same as HW 005
target: -z, pos 6 (strip: p-0, n-0);

NOTE: results shown in the attachments has been evaluated with cmc containing 128 strip
 

Entry  Fri Jun 5 23:39:49 2015, Hao Yin, Belle II FADC (H6A), Hardware, 005, ~200k, 5, No, Good 21x

FIRRun002, pedestalrun005, room temp
Target BW: beam spot at ~ (0 p, 0 n)

Entry  Fri Jun 5 23:38:51 2015, Hao Yin, Belle II FADC (H6A), Pedestal, 005, 10000, , , Unknown 

Readjust after cooling box.

room temp, firrun002
 

Entry  Fri Jun 5 19:59:44 2015, Hao Yin, Belle II FADC (H6A), Pedestal, 004, 10000, , , Good 

update pedestal values for room temp sixlet runs.
 

Entry  Fri Jun 5 19:55:00 2015, Hao Yin, Belle II FADC (H6A), Sixlet Calibration, 003, , , , Unknown 

lat = 98

room temp

pedestalrun 003

Entry  Fri Jun 5 12:03:34 2015, Hao Yin, Belle II FADC (H6A), Sixlet Calibration, 002, , , , Good 

lat = 97 to a greater range of lat scan

Entry  Fri Jun 5 12:02:29 2015, Hao Yin, Belle II FADC (H6A), Sixlet Calibration, 001, , , , Good 

room temp max subevent at 2. with lat = 96

Entry  Fri Jun 5 08:20:27 2015, Hao Yin, Belle II FADC (H6A), Hardware, 004, 50000, 4, No, Good 16x

room temp, FIRRun002, pedestalrun003, taget FW

Entry  Thu Jun 4 22:07:16 2015, Hao Yin, Belle II FADC (H6A), Hardware, 003, 189k, 3, No, Good 21x

CE. pedestal run 003. Fir run 002. Room temp

Entry  Thu Jun 4 18:49:03 2015, Benedikt Würkner, SVD3 (H6B), Setup, , , , , Unknown IMG_20150604_184442.jpgIMG_20150604_184451.jpgIMG_20150604_184516.jpg
 
Entry  Thu Jun 4 18:45:42 2015, Hao Yin, Belle II FADC (H6A), Pedestal, 003, 10000, , , Good 

firrun003, room temp
 

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