Home CMS Production Clean room MedAustron HEPHY testbeams old
testbeam-RD50-DESY-Jul2023 testbeam-RD50-CERN-Oct2022 testbeam-DESY-Oct2017 testbeam-DESY-April2017 testbeam-SPS2015 testbeam-SPS2014 testbeam-DESY14 testbeam-SPS12 testbeam-SPS11 testbeam-SPS10 testbeam-SPS09 testbeam-SPS08 LP-TPC
  HEPHY logbook for testbeam at SPS June 2008, Page 1 of 4  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
ID Date Authorup Project Subject Run Number Events StartTime EndTime Text Attachments
  34   Sun Jun 1 23:36:21 2008 Christian IrmlerSiLCHowTo analyse data    The analysis consists of two stages: 
[LIST]
[*] The first is zero supression an cluster
 analysis_howto.jpg 
  27   Sun Jun 1 15:52:03 2008 Eudet TelescopeSiLCTelescope Pedestal Runrun273812471.6.2008. 15:501.6.2008. 15:58Telescope Pedestal Run
no DUTs!
no Beam!
  
  31   Sun Jun 1 20:13:37 2008 Eudet TelescopeSiLCBZIP2 compressed APVDAQ data    [b]Processed APVDAQ data_cluster - in tar.bzip2
format:[/b]
  
  59   Tue Jun 3 12:41:22 2008 Eudet Telescope useful eudaq software commands(work in progress)   [b]to show information about a run (number
of events, start and end timestamp,....:[/b]
./TestReader.exe -b -e 2828
  
  12   Fri May 30 10:36:18 2008 Marko DragicevicotherImportant Information/Contact    [B]IPs[/B]
Linksys Router
[LIST]
  
  4   Fri May 9 11:46:36 2008 Markus FriedlSiLCData file format(work in progress)   APVDAQ Data Analysis
====================
  
  7   Wed May 14 16:15:30 2008 Markus FriedlBELLEMicron DDD5 Photos    This is the new Micron DDD5 double-sided module
with 3+3 APV25 readout chips on each side.
 micron_pside.jpgmicron_nside.jpgmicron_pside_detail.jpgmicron_nside_detail.jpg 
  8   Mon May 19 15:14:40 2008 Markus FriedlotherTentative Beam Test Schedule    Wed 28 May: ~16:00 arrival, unpacking
Thu 29 May: installation
Fri 30 May: beam on
  
  9   Mon May 19 15:21:49 2008 Markus FriedlotherCERN SPS page 1    SPS Status
SPS
Page 1 - http://hpslweb.cern.ch/frame/java/1.1/view110-java.html
  
  10   Fri May 23 15:17:49 2008 Markus FriedlSiLCModule/chip/strip/zone numbering scheme(work in progress)   The SILC DUT is a stack of 8 silicon sensors
surrounded by the telescope.
The spacing between each of the 8 layers
 telescope_single_dut.giftelescope_8_dut.gifsilc_dut_stack_beam.jpgsilc_dut_beam.jpg 
  11   Mon May 26 15:38:53 2008 Markus FriedlSiLCHow to run APVDAQ    Power-on Procedure
==================
 panel_instruction.gifcern08_silc_all_single.cfgcern08_silc_all_multi6.cfgcern08_silc_mod03_single.cfgcern08_silc_mod03_multi6.cfg 
  16   Sat May 31 17:29:40 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run27162000031.05.2008 14:59:2631.05.2008 15:56:23SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples
trigger: 9 mm opening, TLUControl.exe -d
  
  17   Sat May 31 17:32:35 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup) run2717649031.05.2008 15:57:5831.05.2008 16:09:21SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples
trigger: 9 mm opening, TLUControl.exe -d
  
  18   Sat May 31 17:36:14 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run271810000031.05.2008 16:21:5731.05.2008 21:08:32SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor
stage :=+2 mm
  
  20   Sat May 31 22:54:29 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run271910000031.05.2008 22:34:3801.06.2008 01:49:30SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor
stage :=-2.75 mm
  
  21   Sun Jun 1 01:56:47 2008 Markus FriedlSiLCAPVDAQ + telescope (0-sup)run272010000001.06.2008 01:51:4501.06.2008 07:48:09SiLC beam test - CERN SPS June 2008
8 modules, HV=100V, 40MHz, 6 samples, hor
stage :=-7.5 mm
  
  23   Sun Jun 1 14:36:23 2008 Markus FriedlSiLCAPVDAQ only (0-sup)run000210000001.06.2008 14:25:4301.06.2008 14:54:14SiLC beam test - CERN SPS June 2008 - HIT
MODE
8 modules, HV=100V, 40MHz, 6 samples, hor
  
  24   Sun Jun 1 14:58:53 2008 Markus FriedlSiLCAPVDAQ onlyped0021000001.06.2008 14:55:3101.06.2008 14:59:06SiLC beam test - CERN SPS June 2008 - PEDESTAL
8 modules, HV=100V, 40MHz, 6 samples, hor
stage :=-7.5 mm
  
  25   Sun Jun 1 15:02:51 2008 Markus FriedlSiLCAPVDAQ onlyped0031000001.06.2008 15:00:5401.06.2008 15:04:14SiLC beam test - CERN SPS June 2008 - PEDESTAL
with beam
8 modules, HV=100V, 40MHz, 6 samples, hor
  
  26   Sun Jun 1 15:08:17 2008 Markus FriedlSiLCAPVDAQ only (0-sup)run000310000001.06.2008 15:05:5101.06.2008 15:33:58SiLC beam test - CERN SPS June 2008 - HIT
MODE
8 modules, HV=100V, 40MHz, 6 samples, hor
  
ELOG V3.1.5-fc6679b