Everything works except L3 p-side.
The config file is shown in the following:
### Original Configuration File Name: /home/katsuro/tuxdaq_devel/config/delay_scan.latency_scan.cfg ###
### Original Configuration File Name: /home/katsuro/tuxdaq_devel/config/delay_scan.updated.cfg ###
#
# This is the default config file for the APV_BELLE software
#
#
# Lines preceded by a # or ; sign are ignored.
#
# [rem] comments a whole section until the next section start marked by [xxx] .
#
[soc]
ena = 0
addr =
port = 9999
# [vme]
# VME addresses are given in the format
# {module_name} = {vme_module_number},{vme_address_hex}
# nec ... NECO module
# adf ... particular FADC module
#
# Please note that the address ranges are not defined here,
# they are implicitly given by the hardware.
# Module numbers must fill from 0 (this is not checked).
# Please note that no range checking is performed.
# There is no access to VME modules that are not included in this list,
[vme]
nec = 0,0xaa000000
# p side
adf = 0,0x01000000
adf = 1,0x81000000
# n side
# [nec]
# NECO related information
# mod = 0|1,{shift_register_delay},{adc_range},{win_delay},{win_length},{dead_time},{time_lat},{max_trg}
# (default: 0,75,0,50?,900?,36,2,1)
# res = {list of entries in reset sequence} (default: 2,4)
# cal = {list of entries in cal sequence} (default: 2,3,250,251)
# sw5 = {list of entries in single cal sequence} (default: 2,3)
# str = {list of entries in software trigger sequence} (default: 75)
# htr = {list of entries in hardware trigger sequence} (default: 74)
#
# mod specifies to use either the sequencer (0) or the shift register (1) for hardware trigger and the
# delay of the shift register (0..255); adc_range (0=1Vpp, 1=2Vpp) -- ignored; win_delay and win_length define
# the starting point (relative to the APV trigger) and length of the ADC gate in transparent mode; dead_time is
# the number of 254MHz clock cycles which are set to zero for time measurement after an incoming trigger;
# time_lat is the latency for time measurement in terms of 40MHz clock cycles; max_trg is the number of incoming
# triggers which required to activate the veto logic (usually 1; 0 completely disables the veto logic)
# res, cal, sw5, str and htr are containing the bits to set in the 256-element sequencer memory (nothing is set at -1)
# Please note that cal+str together produce a calibration request plus subsequent normal trigger, so the time
# between them is the latency. sw5 is used to send a single cal request to achieve the correct polarity in
# case the APV inverter is turned on (this feature only works for entire MAMBOs halves = groups of 3 REBOs)
#
# These settings are quite fragile! Do not modify until you know exactly what you are doing.
[nec]
# 30m cables, 40mhz, Tp=50ns, single-trigger
#mod = 0,75,0,70,250,36,2,1
#htr = 64,-1,-1,-1,-1,-1,-1,-1
#str = 100,-1,-1,-1,-1,-1,-1,-1
# TESTBEAM Nov 07, 30m cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
# mod = {0:max triggers, 1:latency, 2:software trigger latency, do not care about the rest}
mod = 0,120,250,0,0,0,0,0
stp = 150,-1,-1,-1,-1,-1,-1,-1
stn = 150,-1,-1,-1,-1,-1,-1,-1
#common settings
rep = 2,-1,-1,-1,-1,-1,-1,-1
ren = 2,-1,-1,-1,-1,-1,-1,-1
cap = 2,52,-1,-1,-1,-1,-1,-1
can = 52,250,-1,-1,-1,-1,-1,-1
# location of file to fir filter can be rel. path
[fir]
# enable fir 1 true otherwise false
ena = 0
# path to fir coef file
pat = /mnt/data/LabLadder5/FIR_L5_class_b-_20150429153730.fir
# [daq]
# DAQ related specifications are given in the format
# ads = {N},{search_max_subevents},0,x
# ini = {initevents},{readout_mode},0,x
# deh = {module_position},{apv_position},0,x
# i2t = {N},0,0,x
# pat = 0,0,0,{data_file_path}
# clk = {N},{Delay25 frequency range},0,x
# pdl = {Trigger input delay},0,0,x
# crd = {crate_number},{clkdel},{trgdel},x
#
# ads N gives the number of samples that are read out from the FIFO1 in transparent mode, search_max_subevents is the
# maximum number of subevents to search for within one ADC stream (default=1).
# ini: initevents is the number of software triggers in the beginning of a run for pedestal and noise
# evaluation. At the beginning of each run, 2*initevents are generated by software, after that the
# selected trigger source (hardware, software of calibration) is activated. The initial evaluation
# events are written to disk as normal events are.
# ini: readout_mode defines whether events beyond the initevents are read in raw transparent mode from FIFO1 (0) or
# in processed mode (1) where only hit information is read from FIFO3
# deh is the APV chip for which single strip histograms are recorded
# i2t is the maximum number of I2C retries in case of failure
# pat specifies the save path for data files (must include a trailing backslash!)
# clk gives the system clock period in integer ns (25 max.) and the frequency range for the Delay25 chip:
# 0...40 MHz, 1...80 MHz, 2...32 MHz, 3...64 MHz
# pdl specifies the delay setting for the trigger input in 0.5ns steps (0..49)
# crd define the global clock and trigger delays between NECO and SVD3_buffer for crates 0 and 1
# NOTE: clock and trigger is NOT propagated to any crate(s) NOT specified here
[daq]
# TESTBEAM Nov 07
#Standard
#ads = 600,3,0,x
# TESTBEAM Nov 07
#Multitrigger (6)
#~ ads = 940,6,0,x
ads = 250,1,0,x
# RAW (transparent mode) readout
ini = 300,0,0,x
# PROCESSED readout
#ini = 300,1,0,x
deh = 1,0,0,x
i2t = 5,0,0,x
pat = 0,0,0,/mnt/data/LabLadder5
#standard 40mhz clock (25ns)
clk = 25,0,0,x
pdl = 25,0,0,x
#crate distribution delays (set to mid-range to allow adjustments in both directions)
crd = 0,25,25,x
#we don't use crate 1, so we don't set any delay here -> no clock/trigger to crate 1
###crd = 1,25,25,x
# [hit]
# Hit recognition variables are specified here
# hcs = {hitcut_/home/hao/Desktop/vme_tests/vme_test_caen/Releaseseed_strip},{hitcut_neighbor_strips}
# nok = {x.x},0
#
#
# hcs gives seed and neighbor hit cuts in units of strpAPVip sigma
# nok states the threshold over average noise at which strips are excluded from further analysis (to exclude noisy strips)
[hit]
# si sensor
hcs = 5.0,3.0
# do not exclude strips
nok = 2000.0,0
# [cal]
# Calibration related data
# lvl = {level},0
# lat = {latbeg},{latend}
# sam = {average_samples},{number of samples in 6-tuple mode}
# grp = {number_of_groups},0
# lg6 = {latency},{group}
# lv6 = {startlevel},{endlevel}
#
# lvl is the CLVL amplitude (0..255), 1 is 625e-, 36 is 1 MIP (22500e-) nominally, in reality 26 is 1 MIP
# lat is the Latency range to
#~ cover (latend-latbeg>=2, latend-latbeg<=15)
# sam is the number of samples to average per position for normal and 6-tuple modes
# grp is how many groups to scan (<=8), first group is strips 0,8,16,..., second group is 1,9,17,..., ...
# lg6 defines the latency in 6-tuple mode and which group to observe in that mode
# lv6 defines the scan range of amplitude in 6-tuple mode
[cal]
#real 1 MIP level (22400e)
lvl = 26,0
#real 5 MIPs level
#lvl = 130,0/home/hao/Desktop/vme_tests/vme_test_caen/Release
#LAT=95/98 Calibration (short display)
#lat = 89,100
#LAT=95/98 Calibration (short display for >=50mhz)
#lat = 81,98
#LAT=95/98 Calibration (long peak mode tail display)
lat = 75,100
#common settings
sam = 50,150
grp = 8,0
#6-tuple mode settings
lg6 = 97, 1
#lv6 = 1,95
lv6 = 50,52
# [i2c]
# This section defines one or more I2C sets for the APV25. In the [mod] section, those sets are referenced to by their number.
# ia2 = {number},{mode},{lat},{ipre},{ipcasc},{ipsf},{isha},{issf},{ipsp},{imuxin},{vfp},{vfs},{vpsp},{muxgain}
#
# The I2C settings must be individually numbered (ascending from 0). The easiest case is to use the same
# settings for all chips of one type, but one could go so far to use separate settings for each chip.
# vadj/vpsp is set individually for each apv in the [mod] section, the value specified here is meaningless.
[i2c]
# apv25s1, peak, inverter ON, Tp=50ns, (p side)
ia2 = 0, 63, 23, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, peak, inverter OFF, Tp=50ns, (n side)
ia2 = 1, 31, 23, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, multi-peak, inverter ON, Tp=50ns, (p side)
#~ ia2 = 0, 61, 17, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side)
#~ ia2 = 1, 29, 17, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, peak, inverter ON, Tp=50ns, (p side), for cooled APV chips, -10C
#~ ia2 = 0, 61, 17, 85, 45, 30, 50, 30, 48, 30, 30, 50, 0, 4
# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side), for cooled APV chips, -10C
#~ ia2 = 1, 29, 17, 85, 45, 30, 34, 30, 48, 30, 30, 60, 0, 4
# [mod]
# Detector module (actually hybrid) specifications are given in the format
# mod = {module_position},{crate_number},{fadc_number},{adc_number},{hybrid_number},m,{adc_delay},0,0,0,0,0,0,{Name}
# apv = {module_position},{apv_position},{i2c_address},{i2c_settings},{vadj/vpsp},x,0,0,{fadc_offset},{fadc_number},{fadc_channel},{fadc_clkdelay [0..49]},{AD8128_gain},x
#
# mod gives the hybrid/module properties: The position counts from 0 to 7 in beam direction,
# Name must not contain blanks ("_" is allowed).
# apv describes the chips located on a hybrid
# and the ADC channel where they are read out, either a Vienna ADC (a) or a FED (f).
# The ADC offset is only available with the Vienna ADCs and shifts the baseline.
#~ # The individual chip vadj setting dominates over the [i2c] setting.
# p-side
[mod]
mod = 1,0,0,0,0,m,24,0,0,0,0,0,0,fw_p
apv = 1,0,34,0,30,x,0,0,0,0,0,0,0,x
apv = 1,1,36,0,30,x,0,0,0,0,1,0,0,x
apv = 1,2,38,0,30,x,0,0,0,0,2,0,0,x
apv = 1,3,40,0,30,x,0,0,0,0,3,0,0,x
apv = 1,4,42,0,30,x,0,0,0,0,4,0,0,x
#~ apv = 1,5,44,0,30,x,0,0,0,0,5,0,0,x
[mod]
mod = 2,0,0,1,1,m,38,0,0,0,0,0,0,ce_p
apv = 2,0,34,0,30,x,0,0,0,0,6,0,0,x
apv = 2,1,36,0,30,x,0,0,0,0,7,0,0,x
apv = 2,2,38,0,30,x,0,0,0,0,8,0,0,x
apv = 2,3,40,0,30,x,0,0,0,0,9,0,0,x
apv = 2,4,42,0,30,x,0,0,0,0,10,0,0,x
apv = 2,5,44,0,30,x,0,0,0,0,11,0,0,x
[mod]
mod = 3,0,0,2,2,m,40,0,0,0,0,0,0,-z_p
apv = 3,0,34,0,30,x,0,0,0,0,12,0,0,x
apv = 3,1,36,0,30,x,0,0,0,0,13,0,0,x
apv = 3,2,38,0,30,x,0,0,0,0,14,0,0,x
apv = 3,3,40,0,30,x,0,0,0,0,15,0,0,x
apv = 3,4,42,0,30,x,0,0,0,0,16,0,0,x
apv = 3,5,44,0,30,x,0,0,0,0,17,0,0,x
[mod]
mod = 4,0,0,3,3,m,24,0,0,0,0,0,0,bw_p
apv = 4,0,34,0,30,x,0,0,0,0,18,0,0,x
apv = 4,1,36,0,30,x,0,0,0,0,19,0,0,x
apv = 4,2,38,0,30,x,0,0,0,0,20,0,0,x
apv = 4,3,40,0,30,x,0,0,0,0,21,0,0,x
apv = 4,4,42,0,30,x,0,0,0,0,22,0,0,x
apv = 4,5,44,0,30,x,0,0,0,0,23,0,0,x
[mod]
#~ mod = 5,0,0,4,4,m,24,0,0,0,0,0,0,L3_p
#~ apv = 5,0,34,0,30,x,0,0,0,0,24,0,0,x
#~ apv = 5,1,36,0,30,x,0,0,0,0,25,0,0,x
#~ apv = 5,2,38,0,30,x,0,0,0,0,26,0,0,x
#~ apv = 5,3,40,0,30,x,0,0,0,0,27,0,0,x
#~ apv = 5,4,42,0,30,x,0,0,0,0,28,0,0,x
#~ apv = 5,5,44,0,30,x,0,0,0,0,29,0,0,x
[mod]
mod = 6,0,0,5,5,m,24,0,0,0,0,0,0,L4_p
apv = 6,0,34,0,30,x,0,0,0,0,30,0,0,x
apv = 6,1,36,0,30,x,0,0,0,0,31,0,0,x
apv = 6,2,38,0,30,x,0,0,0,0,32,0,0,x
apv = 6,3,40,0,30,x,0,0,0,0,33,0,0,x
apv = 6,4,42,0,30,x,0,0,0,0,34,0,0,x
apv = 6,5,44,0,30,x,0,0,0,0,35,0,0,x
[mod]
mod = 7,0,0,6,6,m,24,0,0,0,0,0,0,L5_p
apv = 7,0,34,0,30,x,0,0,0,0,36,0,0,x
apv = 7,1,36,0,30,x,0,0,0,0,37,0,0,x
apv = 7,2,38,0,30,x,0,0,0,0,38,0,0,x
apv = 7,3,40,0,30,x,0,0,0,0,39,0,0,x
apv = 7,4,42,0,30,x,0,0,0,0,40,0,0,x
apv = 7,5,44,0,30,x,0,0,0,0,41,0,0,x
[mod]
mod = 8,0,0,7,7,m,24,0,0,0,0,0,0,L6_p
apv = 8,0,34,0,30,x,0,0,0,0,42,0,0,x
apv = 8,1,36,0,30,x,0,0,0,0,43,0,0,x
apv = 8,2,38,0,30,x,0,0,0,0,44,0,0,x
apv = 8,3,40,0,30,x,0,0,0,0,45,0,0,x
apv = 8,4,42,0,30,x,0,0,0,0,46,0,0,x
apv = 8,5,44,0,30,x,0,0,0,0,47,0,0,x
#---------------------------------------------------- n-side
[mod]
mod = 9,0,1,0,0,m,28,0,0,0,0,0,0,fw_n
apv = 9,0,34,1,30,x,0,0,5,1,0,0,0,x
apv = 9,1,36,1,30,x,0,0,5,1,1,0,0,x
apv = 9,2,38,1,30,x,0,0,5,1,2,0,0,x
apv = 9,3,40,1,30,x,0,0,5,1,3,0,0,x
[mod]
mod = 10,0,1,1,1,m,33,0,0,0,0,0,0,ce_n
apv = 10,0,34,1,30,x,0,0,5,1,6,0,0,x
apv = 10,1,36,1,30,x,0,0,5,1,7,0,0,x
apv = 10,2,38,1,30,x,0,0,5,1,8,0,0,x
apv = 10,3,40,1,30,x,0,0,5,1,9,0,0,x
[mod]
mod = 11,0,1,2,2,m,35,0,0,0,0,0,0,-z_n
apv = 11,0,34,1,30,x,0,0,5,1,12,0,0,x
apv = 11,1,36,1,30,x,0,0,5,1,13,0,0,x
apv = 11,2,38,1,30,x,0,0,5,1,14,0,0,x
apv = 11,3,40,1,30,x,0,0,5,1,15,0,0,x
[mod]
mod = 12,0,1,3,3,m,27,0,0,0,0,0,0,bw_n
apv = 12,0,34,1,30,x,0,0,5,1,18,0,0,x
apv = 12,1,36,1,30,x,0,0,5,1,19,0,0,x
apv = 12,2,38,1,30,x,0,0,5,1,20,0,0,x
apv = 12,3,40,1,30,x,0,0,5,1,21,0,0,x
[mod]
mod = 13,0,1,4,4,m,24,0,0,0,0,0,0,L3_n
#~ apv = 13,0,34,0,30,x,0,0,0,1,24,0,0,x
apv = 13,1,36,0,30,x,0,0,0,1,25,0,0,x
apv = 13,2,38,0,30,x,0,0,0,1,26,0,0,x
apv = 13,3,40,0,30,x,0,0,0,1,27,0,0,x
apv = 13,4,42,0,30,x,0,0,0,1,28,0,0,x
#~ apv = 13,5,44,0,30,x,0,0,0,1,29,0,0,x
[mod]
mod = 14,0,1,5,5,m,24,0,0,0,0,0,0,L4_n
apv = 14,0,34,0,30,x,0,0,0,1,30,0,0,x
apv = 14,1,36,0,30,x,0,0,0,1,31,0,0,x
apv = 14,2,38,0,30,x,0,0,0,1,32,0,0,x
apv = 14,3,40,0,30,x,0,0,0,1,33,0,0,x
#~ apv = 14,4,42,0,30,x,0,0,0,1,34,0,0,x
#~ apv = 14,5,44,0,30,x,0,0,0,1,35,0,0,x
[mod]
mod = 15,0,1,6,6,m,24,0,0,0,0,0,0,L5_n
apv = 15,0,34,0,30,x,0,0,0,1,36,0,0,x
apv = 15,1,36,0,30,x,0,0,0,1,37,0,0,x
apv = 15,2,38,0,30,x,0,0,0,1,38,0,0,x
apv = 15,3,40,0,30,x,0,0,0,1,39,0,0,x
#~ apv = 15,4,42,0,30,x,0,0,0,1,40,0,0,x
#~ apv = 15,5,44,0,30,x,0,0,0,1,41,0,0,x
[mod]
mod = 16,0,1,7,7,m,24,0,0,0,0,0,0,L6_n
apv = 16,0,34,0,30,x,0,0,0,1,42,0,0,x
apv = 16,1,36,0,30,x,0,0,0,1,43,0,0,x
apv = 16,2,38,0,30,x,0,0,0,1,44,0,0,x
apv = 16,3,40,0,30,x,0,0,0,1,45,0,0,x
#~ apv = 16,4,42,0,30,x,0,0,0,1,46,0,0,x
#~ apv = 16,5,44,0,30,x,0,0,0,1,47,0,0,x |