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Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 5 of 6 |
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Mon Nov 17 23:04:57 2014, Hao Yin, Belle SVD, PedestalRun_002, , 10338, Mon Nov 17 23:03:03 CET 2014, , Unknown
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Tue Nov 18 01:03:18 2014, Hao Yin, Belle SVD, Remapped FADC inputs, , , Tue Nov 18 01:03:32 CET 2014, , Unknown
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Tue Nov 18 01:05:04 2014, Hao Yin, Belle SVD, PedestalRun_003, , , Tue Nov 18 01:03:32 CET 2014, , Unknown
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Tue Nov 18 09:48:53 2014, Hao Yin, Belle SVD, PedestalRun_004, , 10000, Tue Nov 18 09:48:30 CET 2014, , Unknown
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Tue Nov 18 09:51:11 2014, Hao Yin, , CalibrationRun_002, , , Tue Nov 18 09:50:24 CET 2014, , Unknown
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Tue Nov 18 10:12:25 2014, Hao Yin, Belle SVD, 6let PedestalRun_005, , 10000, Tue Nov 18 10:11:45 CET 2014, , Unknown
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Tue Nov 18 10:26:56 2014, Hao Yin, Belle SVD, CalibrationRun_003, , , Tue Nov 18 10:26:52 CET 2014, , Unknown
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Tue Nov 18 12:35:32 2014, Axel König, common, Infineon (4 modules) TLU Settings, , , , , Unknown
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Tue Nov 18 18:45:01 2014, Hao Yin, Belle SVD, Trigger Delay scan, , , Tue Nov 18 18:21:50 CET 2014, , Unknown
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Tue Nov 18 20:26:12 2014, Hao Yin, Belle SVD, HardwareRun_001, , , Tue Nov 18 18:21:50 CET 2014, , Unknown
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Tue Nov 18 20:42:18 2014, Benedikt Würkner, Belle SVD, Coordinates of the DUT, , , , , Unknown
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Wed Nov 19 16:24:25 2014, Axel König, common, Running EUDAQ, , , , , Unknown
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Wed Nov 19 20:04:53 2014, Hao Yin, Belle SVD, PedestalRun_006, , , , , Unknown
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Wed Nov 19 20:07:05 2014, Hao Yin, Belle SVD, HardwareRun_002, , , , , Unknown
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Wed Nov 19 22:25:29 2014, Hao Yin, Belle SVD, PedestalRun_008 [CheckLayout], , , , , Unknown
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Wed Nov 19 22:59:24 2014, Hao Yin, Belle SVD, CalibrationRun_004, , , , , Crap
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Wed Nov 19 23:15:50 2014, Hao Yin, Belle SVD, HardwareRun_003, , , , , Unknown
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Wed Nov 19 23:31:08 2014, Hao Yin, Belle SVD, HardwareRun_004, , , , , Unknown
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Thu Nov 20 00:52:50 2014, Hao Yin, Belle SVD, FIRRun_002, , , , , Unknown
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Thu Nov 20 00:54:21 2014, Hao Yin, Belle SVD, PedestalRun_008, , , , , Unknown
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