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  Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 6 of 6  Not logged in ELOG logo
Entry  Sun Nov 23 12:55:47 2014, Benedikt Würkner, Belle SVD, HardwareRun, 045, 20000, , , Unknown 

Hardware Run +-50V Bias

Room Temperature

Pedestal 018 (again marked all the bad strips)

Zero Suppressed

Entry  Sun Nov 23 15:07:54 2014, Markus Friedl, Belle SVD, common, , , , , Unknown fwbw_setup.png

Geometry setup of FW/BW:

(all dimensions are in mm and refer to the sensor planes)

Entry is currently edited by Thomas Bergauer on 193.170.243.91  Entry  Sun Nov 23 17:51:44 2014, Benedikt Würkner, Belle SVD, HardwareRun, 046, 100000, 20:06, 20:36, Unknown 

Hardware Run +-60V Bias

Room Temperature

Pedestal 018 (again marked all the bad strips)

Zero Suppressed

 

Entry  Mon Nov 17 22:21:41 2014, Hao Yin, , FIR run, 001, , Mon Nov 17 22:08:29 CET 2014, , Good 

Excellent, brilliant run. 

Entry  Thu Nov 20 22:11:06 2014, Hao Yin, Belle SVD, HardwareRun, 012, , , , Good 

cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode

FIFO size increased

Entry  Fri Nov 21 19:42:36 2014, Hao Yin, , HardwareRun_033, , , , , Good Temp_21-11-14.PNG

L6 are swapped, needs to be corrected later in the offline analysis.

cooled at -25

latest ADC delay and FIRRun

PedestalRun_012

CalibrationRun_006

100k trigger dead time

 

Need to change L6n apv definition to:

mod = 9,0,1,1,1,m,29,0,0,0,0,0,0,L6_n_side

apv = 9,1,34,3,30,x,0,0,5,1,7,0,0,x
apv = 9,0,36,3,50,x,0,0,5,1,6,0,0,x
apv = 9,3,38,3,30,x,0,0,5,1,9,0,0,x
apv = 9,2,40,3,30,x,0,0,5,1,8,0,0,x

to  get the right mapping of the sensor.

Entry  Sun Nov 23 15:09:53 2014, Markus Friedl, Belle SVD, PedestalRun, 001, 10000, , , Good 

Initial pedestal run with SVD3 setup and WedgeOld, FW993, BW993 (reading out 4 chips on every p-side)

Entry  Sun Nov 23 15:10:42 2014, Markus Friedl, Belle SVD, CalibrationRun, 001, 83400, , , Good 

Initial calibration run with SVD3 setup and WedgeOld, FW993, BW993 (reading out 4 chips on every p-side)

Entry  Sun Nov 23 15:13:37 2014, Markus Friedl, Belle SVD, HardwareRun, 003, 100600, 23.11.2014 14:07:23, 23.11.2014 16:51:27, Good 

Hardware run, hitting APVs 0/1 on p-sides, 1/2 on n-sides

EUDAT telescope running with difference of 2 events

Entry  Sun Nov 23 16:55:37 2014, Markus Friedl, Belle SVD, HardwareRun, 004, 60600, 23.11.2014 16:51:49, 23.11.2014 18:23:54, Good 

Hardware run, hitting APVs 1/2 on p-sides, 1/2 on n-sides

EUDAT telescope running with difference of 2 events

Entry  Sun Nov 23 18:26:54 2014, Markus Friedl, Belle SVD, HardwareRun, 005, 60600, 23.11.2014 18:24:34, 23.11.2014 , Good 

Hardware run, hitting APVs 2/3 on p-sides, 1/2 on n-sides

EUDAT telescope running with difference of 2 events

Entry  Wed Nov 19 22:59:24 2014, Hao Yin, Belle SVD, CalibrationRun_004, , , , , Crap 

cooled (see last calibration run)

Latest noise, FIRfilter settings. 

 

Failed due to VME read timeout.

Entry  Thu Nov 20 11:13:44 2014, Hao Yin, , HardwareRun_008, 008, , , , Crap 

cooled see attachment in FIRRun_003

PedestalRun_009

CalibrationRun_005

zerosuppressed

Entry  Thu Nov 20 11:14:19 2014, Benedikt Würkner, , HardwareRun_009, 009, , , , Crap 

 cooling see attachment of FIRRun003

Ped 009

Cal 005

Multi 6 raw mode

L5_n_side out of order

 

FIFO_FULL_ERROR starting at ~2000 events

Entry  Thu Nov 20 15:32:33 2014, Hao Yin, , HardwareRun, 010, , , , Crap 

same as hardware run 009

FIFO FULL ERROR starting at ~event 5000

Entry  Thu Nov 20 16:13:18 2014, Hao Yin, Belle SVD, HardwareRun, 011, , , , Crap 

cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode

FIFO size increased

 

 

FIFO FULL at  event ~27000

Entry  Fri Nov 21 15:10:19 2014, Benedikt Würkner, , HardwareRun, 15-22 (exept 19) , none, , , Crap 
 
Entry  Sun Nov 23 01:05:43 2014, Hao Yin, Belle SVD, HardwareRun, 039, 20000, 2014-11-22 15:18:40, , Crap 

Cooled down to -20

Bias voltage set to +-80V

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

 

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