Temperature: See attachment
FIRFilterRun_002
Layer 3-n side deactivated, because Hao broke it.
Multi-6 cooled.
See latest Noise, and PedestalRun.
cooled (temperature see attachment latest noise run),
latest Noise, FIR settings with the right layout mapping.
cooled (see last calibration run)
Latest noise, FIRfilter settings.
Failed due to VME read timeout.
cooled, latest noise, cal, PedestalRun.
Rawmode
Same as HardwareRun_003 but with ZS.
cooled with new delay run
temp see attachment (von flo) 10000 latest fir filter (002)
temp cooled see attachment
last noise run(007)
FIRRun_002
PedestalRun_008
new cal run Raw, test with put fifo full flags
Cooled see appendix
with new layout (l3_n-side channels changed and reactivated).
Latest FIRRun
cooled see appendix (FIRRun003)
MaxEvents 10000
cooled see appendix (FIRRun_003)
PedestalRun_009
cooled see attachment in FIRRun_003
CalibrationRun_005
zerosuppressed
cooling see attachment of FIRRun003
Ped 009
Cal 005
Multi 6 raw mode
L5_n_side out of order
FIFO_FULL_ERROR starting at ~2000 events
same as hardware run 009
FIFO FULL ERROR starting at ~event 5000
Infineon new stack - batch 4
cooled see appendix (FirRun003)
multi 6 Raw Mode
FIFO size increased
FIFO FULL at event ~27000