same as hardware run 009
FIFO FULL ERROR starting at ~event 5000
cooling see attachment of FIRRun003
Multi 6 raw mode
L5_n_side out of order
FIFO_FULL_ERROR starting at ~2000 events
cooled see attachment in FIRRun_003
cooled see appendix (FIRRun_003)
cooled see appendix (FIRRun003)
Cooled see appendix
with new layout (l3_n-side channels changed and reactivated).
temp cooled see attachment
last noise run(007)
new cal run Raw, test with put fifo full flags
temp see attachment (von flo)
latest fir filter (002)
cooled with new delay run
Same as HardwareRun_003 but with ZS.
cooled, latest noise, cal, PedestalRun.
cooled (see last calibration run)
Latest noise, FIRfilter settings.
Failed due to VME read timeout.
cooled (temperature see attachment latest noise run),
latest Noise, FIR settings with the right layout mapping.
Infineon new stack - batch 4
See latest Noise, and PedestalRun.
Temperature: See attachment
Layer 3-n side deactivated, because Hao broke it.