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  Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 4 of 6  Not logged in ELOG logo
ID Date Author Projectup Subject Run Number Events StartTime EndTime Data
  66   Thu Nov 20 22:11:06 2014 Hao YinBelle SVDHardwareRun012   Good

cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode

FIFO size increased

  71   Fri Nov 21 15:02:28 2014 Benedikt WürknerBelle SVDHardwareRun0131433  Unknown

cooled see appendix (FirRun003)
PedestalRun_010
multi 6 Raw Mode
FIFO size increased
L3n deactivated
100000 deadtime (CTRL TRG)
Zero_suppressed

  72   Fri Nov 21 15:03:08 2014 Benedikt WürknerBelle SVDHardwareRun014989  Unknown

cooled see appendix (FirRun003)
PedestalRun_010
multi 6 Raw Mode
FIFO size increased
L3n deactivated
100000 deadtime (CTRL TRG)
Zero_suppressed

  73   Fri Nov 21 15:07:24 2014 Benedikt WürknerBelle SVDHardwareRun0191509482014-11-21 02:41:552014-11-21 10:11:02Unknown

cooled see appendix (FirRun003)
PedestalRun_010
multi 6 Raw Mode
FIFO size increased
L3n deactivated
100000 deadtime (CTRL TRG)

VME Error, overnight run

  80   Fri Nov 21 19:05:27 2014 Hao YinBelle SVDFIRRun_004  Fri Nov 21 19:05:23 CET 2014 Unknown

New ADC delay scan. cooled, -25 temperature

 

  81   Fri Nov 21 19:10:09 2014 Hao YinBelle SVDCalibrationRun_006    Unknown

cooled, latest ADC delay scan and FIRRun. 

  92   Sat Nov 22 11:16:26 2014 Markus FriedlBelle SVDcooling    Unknown

Cooling box plant hung up (I2C error on Alix, persistent after reboot)

Power-cycled cooling plant, now working

Slowly cooling down again

  93   Sat Nov 22 11:37:16 2014 Benedikt WürknerBelle SVDHardwareRun0364503782014-11-22 1:00:002014-11-22 10:27:54Unknown

 Not completely cooled since cooling failed at 1:42 in the night

Bias voltage set to +-60V

Some error with event no17 or 18 leading to the data not being easily analysable requiring a hack in TuxOA

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

Attachment 1: SPS_Testbeam-Temp.xlsx
Attachment 2: Screen_Shot_2014-11-22_at_12.41.44.png
Screen_Shot_2014-11-22_at_12.41.44.png
  94   Sat Nov 22 15:31:49 2014 Hao YinBelle SVDHardwareRun038437882014-11-22 15:18:40 Unknown

Cooled down to -20

Bias voltage set to +-60V

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

Zero suppressed

  105   Sun Nov 23 01:05:43 2014 Hao YinBelle SVDHardwareRun039200002014-11-22 15:18:40 Crap

Cooled down to -20

Bias voltage set to +-80V

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

 

  106   Sun Nov 23 01:37:42 2014 Hao YinBelle SVDHardwareRun040200002014-11-23 01:37:00 Unknown

Bias voltage set to +-80V

Pedestal_015 (cooled)

"New" layout with no cooling (CO2 is no more)

Newly set values for APC Delay

New FIR Run 005

Temperature around 30 C

Bias: +-80V

  109   Sun Nov 23 09:49:00 2014 Markus FriedlBelle SVDcooling    Unknown

Saturday evening, the cooling became unstable which indicates the end of the CO2 supply, possibly having a mixture of liquid and gas phases.

Strange oscillations observed for the DUT temperatures until the MF valve was finally turned off close to midnight.

 

Attachment 1: temp_last_night.png
temp_last_night.png
  110   Sun Nov 23 10:32:41 2014 Hao YinBelle SVDPedestalRun01610000  Unknown

Pedestal Run

room temperature (30C)

Bias scans planned

  111   Sun Nov 23 10:51:49 2014 Hao YinBelle SVDHardwareRun04276863  Unknown

Hardware Run +-40V Bias

Room Temperature

Pedestal 016

Zero Suppressed

Attachment 1: Temp_23-11-14.PNG
Temp_23-11-14.PNG
  112   Sun Nov 23 12:17:59 2014 Benedikt WürknerBelle SVDHardwareRun04420000  Unknown

Hardware Run +-30V Bias

Room Temperature

Pedestal 017 (again marked all the bad strips)

Zero Suppressed

  114   Sun Nov 23 12:55:47 2014 Benedikt WürknerBelle SVDHardwareRun04520000  Unknown

Hardware Run +-50V Bias

Room Temperature

Pedestal 018 (again marked all the bad strips)

Zero Suppressed

  115   Sun Nov 23 15:07:54 2014 Markus FriedlBelle SVDcommon    Unknown

Geometry setup of FW/BW:

(all dimensions are in mm and refer to the sensor planes)

Attachment 1: fwbw_setup.png
fwbw_setup.png
  116   Sun Nov 23 15:09:53 2014 Markus FriedlBelle SVDPedestalRun00110000  Good

Initial pedestal run with SVD3 setup and WedgeOld, FW993, BW993 (reading out 4 chips on every p-side)

  117   Sun Nov 23 15:10:42 2014 Markus FriedlBelle SVDCalibrationRun00183400  Good

Initial calibration run with SVD3 setup and WedgeOld, FW993, BW993 (reading out 4 chips on every p-side)

  118   Sun Nov 23 15:13:37 2014 Markus FriedlBelle SVDHardwareRun00310060023.11.2014 14:07:2323.11.2014 16:51:27Good

Hardware run, hitting APVs 0/1 on p-sides, 1/2 on n-sides

EUDAT telescope running with difference of 2 events

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