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  Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 4 of 6  Not logged in ELOG logo
New entries since:Thu Jan 1 01:00:00 1970
Entry  Thu Nov 20 16:13:18 2014, Hao Yin, Belle SVD, HardwareRun, 011, , , , Crap 

cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode

FIFO size increased

 

 

FIFO FULL at  event ~27000

Entry  Thu Nov 20 22:11:06 2014, Hao Yin, Belle SVD, HardwareRun, 012, , , , Good 

cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode

FIFO size increased

Entry  Fri Nov 21 15:02:28 2014, Benedikt Würkner, Belle SVD, HardwareRun, 013, 1433, , , Unknown 

cooled see appendix (FirRun003)
PedestalRun_010
multi 6 Raw Mode
FIFO size increased
L3n deactivated
100000 deadtime (CTRL TRG)
Zero_suppressed

Entry  Fri Nov 21 15:03:08 2014, Benedikt Würkner, Belle SVD, HardwareRun, 014, 989, , , Unknown 

cooled see appendix (FirRun003)
PedestalRun_010
multi 6 Raw Mode
FIFO size increased
L3n deactivated
100000 deadtime (CTRL TRG)
Zero_suppressed

Entry  Fri Nov 21 15:07:24 2014, Benedikt Würkner, Belle SVD, HardwareRun, 019, 150948, 2014-11-21 02:41:55, 2014-11-21 10:11:02, Unknown 

cooled see appendix (FirRun003)
PedestalRun_010
multi 6 Raw Mode
FIFO size increased
L3n deactivated
100000 deadtime (CTRL TRG)

VME Error, overnight run

Entry  Fri Nov 21 19:05:27 2014, Hao Yin, Belle SVD, FIRRun_004, , , Fri Nov 21 19:05:23 CET 2014, , Unknown 

New ADC delay scan. cooled, -25 temperature

 

Entry  Fri Nov 21 19:10:09 2014, Hao Yin, Belle SVD, CalibrationRun_006, , , , , Unknown 

cooled, latest ADC delay scan and FIRRun. 

Entry  Sat Nov 22 11:16:26 2014, Markus Friedl, Belle SVD, cooling, , , , , Unknown 

Cooling box plant hung up (I2C error on Alix, persistent after reboot)

Power-cycled cooling plant, now working

Slowly cooling down again

Entry  Sat Nov 22 11:37:16 2014, Benedikt Würkner, Belle SVD, HardwareRun, 036, 450378, 2014-11-22 1:00:00, 2014-11-22 10:27:54, Unknown SPS_Testbeam-Temp.xlsxScreen_Shot_2014-11-22_at_12.41.44.png

 Not completely cooled since cooling failed at 1:42 in the night

Bias voltage set to +-60V

Some error with event no17 or 18 leading to the data not being easily analysable requiring a hack in TuxOA

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

Entry  Sat Nov 22 15:31:49 2014, Hao Yin, Belle SVD, HardwareRun, 038, 43788, 2014-11-22 15:18:40, , Unknown 

Cooled down to -20

Bias voltage set to +-60V

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

Zero suppressed

Entry  Sun Nov 23 01:05:43 2014, Hao Yin, Belle SVD, HardwareRun, 039, 20000, 2014-11-22 15:18:40, , Crap 

Cooled down to -20

Bias voltage set to +-80V

Pedestal_013 (cooled)

Noisefile: HardwareRun_036.noi

 

Entry  Sun Nov 23 01:37:42 2014, Hao Yin, Belle SVD, HardwareRun, 040, 20000, 2014-11-23 01:37:00, , Unknown 

Bias voltage set to +-80V

Pedestal_015 (cooled)

"New" layout with no cooling (CO2 is no more)

Newly set values for APC Delay

New FIR Run 005

Temperature around 30 C

Bias: +-80V

Entry  Sun Nov 23 09:49:00 2014, Markus Friedl, Belle SVD, cooling, , , , , Unknown temp_last_night.png

Saturday evening, the cooling became unstable which indicates the end of the CO2 supply, possibly having a mixture of liquid and gas phases.

Strange oscillations observed for the DUT temperatures until the MF valve was finally turned off close to midnight.

 

Entry  Sun Nov 23 10:32:41 2014, Hao Yin, Belle SVD, PedestalRun, 016, 10000, , , Unknown 

Pedestal Run

room temperature (30C)

Bias scans planned

Entry  Sun Nov 23 10:51:49 2014, Hao Yin, Belle SVD, HardwareRun, 042, 76863, , , Unknown Temp_23-11-14.PNG

Hardware Run +-40V Bias

Room Temperature

Pedestal 016

Zero Suppressed

Entry  Sun Nov 23 12:17:59 2014, Benedikt Würkner, Belle SVD, HardwareRun, 044, 20000, , , Unknown 

Hardware Run +-30V Bias

Room Temperature

Pedestal 017 (again marked all the bad strips)

Zero Suppressed

Entry  Sun Nov 23 12:55:47 2014, Benedikt Würkner, Belle SVD, HardwareRun, 045, 20000, , , Unknown 

Hardware Run +-50V Bias

Room Temperature

Pedestal 018 (again marked all the bad strips)

Zero Suppressed

Entry  Sun Nov 23 15:07:54 2014, Markus Friedl, Belle SVD, common, , , , , Unknown fwbw_setup.png

Geometry setup of FW/BW:

(all dimensions are in mm and refer to the sensor planes)

Entry  Sun Nov 23 15:09:53 2014, Markus Friedl, Belle SVD, PedestalRun, 001, 10000, , , Good 

Initial pedestal run with SVD3 setup and WedgeOld, FW993, BW993 (reading out 4 chips on every p-side)

Entry  Sun Nov 23 15:10:42 2014, Markus Friedl, Belle SVD, CalibrationRun, 001, 83400, , , Good 

Initial calibration run with SVD3 setup and WedgeOld, FW993, BW993 (reading out 4 chips on every p-side)

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