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  Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 3 of 6  Not logged in ELOG logo
ID Date Author Projectup Subject Run Number Events StartTime EndTime Data
  26   Tue Nov 18 10:12:25 2014 Hao YinBelle SVD6let PedestalRun_005 10000Tue Nov 18 10:11:45 CET 2014 Unknown

At room temperature

Latest delay, FIRRun002. 

Check for bad strips.

  27   Tue Nov 18 10:26:56 2014 Hao YinBelle SVDCalibrationRun_003  Tue Nov 18 10:26:52 CET 2014 Unknown

At room temperature

Latest delay and FIRRun 

  32   Tue Nov 18 18:45:01 2014 Hao YinBelle SVDTrigger Delay scan  Tue Nov 18 18:21:50 CET 2014 Unknown

At room temperature

First run was at: 23 (no track)



Trigger delay: 26



Trigger delay: 29



Trigger delay: 32



Trigger delay: 20



Trigger delay: 17



Trigger delay: 14
Trigger chip delay: 110




  33   Tue Nov 18 20:26:12 2014 Hao YinBelle SVDHardwareRun_001  Tue Nov 18 18:21:50 CET 2014 Unknown

At room temperature

Latest ADC scan and FIR run.

Latest CAL.


Position: 0.0, see elog entry.

  35   Tue Nov 18 20:42:18 2014 Benedikt WürknerBelle SVDCoordinates of the DUT    Unknown

We set the coordinates trying to put the beam in an area with well working APVs

Peak of course differs for n and p sensors due to their different pitch.

L4-6 n-side Peak around strip 180

L4&6 p-side mean value around strip 380

L5 p-side moved by 4.8mm due to reasons (APV misalignment I think) therefore the peak of the same measurements is moved by 4.8/75µm = 64 strips therefore centered around strip 320

The coordinates of the x-y table were set to 0:0 at this point. Refer to Run Alignment2 for reference data.

  42   Wed Nov 19 20:04:53 2014 Hao YinBelle SVDPedestalRun_006    Unknown

Temperature: See attachment


Layer 3-n side deactivated, because Hao broke it.

Attachment 1: Temp_19-11-14.PNG
  43   Wed Nov 19 20:07:05 2014 Hao YinBelle SVDHardwareRun_002    Unknown

Multi-6 cooled.

See latest Noise, and PedestalRun.


  46   Wed Nov 19 22:25:29 2014 Hao YinBelle SVDPedestalRun_008 [CheckLayout]    Unknown

cooled (temperature see attachment latest noise run),

latest Noise, FIR settings with the right layout mapping.

  47   Wed Nov 19 22:59:24 2014 Hao YinBelle SVDCalibrationRun_004    Crap

cooled (see last calibration run)

Latest noise, FIRfilter settings. 


Failed due to VME read timeout.

  48   Wed Nov 19 23:15:50 2014 Hao YinBelle SVDHardwareRun_003    Unknown

cooled, latest noise, cal, PedestalRun.


  49   Wed Nov 19 23:31:08 2014 Hao YinBelle SVDHardwareRun_004    Unknown

Same as HardwareRun_003 but with ZS.  

  50   Thu Nov 20 00:52:50 2014 Hao YinBelle SVDFIRRun_002    Unknown

cooled with new delay run

  51   Thu Nov 20 00:54:21 2014 Hao YinBelle SVDPedestalRun_008    Unknown

temp see attachment (von flo)
latest fir filter (002)

  52   Thu Nov 20 00:55:14 2014 Hao YinBelle SVDHardwareRun_007    Unknown

temp cooled see attachment

last noise run(007)



new cal run Raw, test with put fifo full flags

  53   Thu Nov 20 10:22:17 2014 Markus FriedlBelle SVDcommon    Unknown
  1. Some VME errors occured over night
  2. Optical fiber changed
  3. Situation improved


  1. L3n hybrid could not be configured by I2C
  2. Plugged cable into the former FWDn slot
  3. Fully working


  54   Thu Nov 20 10:33:13 2014 Benedikt WürknerBelle SVDFIRRun and Delay Scan003   Unknown

 Cooled see appendix

with new layout (l3_n-side channels changed and reactivated).

Latest FIRRun

Attachment 1: Temp_19-11-14.PNG
  55   Thu Nov 20 10:39:11 2014 Benedikt WürknerBelle SVDPedestalRun_009    Unknown

cooled see appendix (FIRRun003)

MaxEvents 10000


  56   Thu Nov 20 10:39:13 2014 Benedikt WürknerBelle SVDPedestalRun_009    Unknown

cooled see appendix (FIRRun003)

MaxEvents 10000


  57   Thu Nov 20 10:41:54 2014 Benedikt WürknerBelle SVDCalibrationRun_005    Unknown

 cooled see appendix (FIRRun_003)


  63   Thu Nov 20 16:13:18 2014 Hao YinBelle SVDHardwareRun011   Crap

cooled see appendix (FirRun003)


multi 6 Raw Mode

FIFO size increased



FIFO FULL at  event ~27000

ELOG V3.1.4-395e101