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Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 2 of 6

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ID	Date	Author	Project	Subject	Run Number	Events	StartTime	Data
13	Mon Nov 17 22:18:27 2014	Hao Yin	Belle SVD	ADC delay scan			Mon Nov 17 22:08:29	Unknown
L3-p: 18 L4-p: 36 L5-p: 33 L6-p: 39 L3-n: 18 L4-n: 36 L5-n: 36 L6-n: 35
14	Mon Nov 17 22:21:41 2014	Hao Yin		FIR run	001		Mon Nov 17 22:08:29 CET 2014	Good
Excellent, brilliant run.
15	Mon Nov 17 22:21:50 2014	Hao Yin		Bad APVs			Mon Nov 17 22:08:29 CET 2014	Unknown
List with bad APVs: Crap: APV 5 L6-p Channel 23 Not working: L3-n APV 3
16	Mon Nov 17 22:22:56 2014	Hao Yin		PedestalRun_001	001	10000	Mon Nov 17 22:22:41 CET 2014	Unknown
At room temperature.
17	Mon Nov 17 22:28:05 2014	Hao Yin		CalibrationRun	001		Mon Nov 17 22:27:07 CET 2014	Unknown
Noise file from run 001 PedestalRun_001 FIRRun_001 At room temperature See DelayRun_001
18	Mon Nov 17 22:28:07 2014	Hao Yin		CalibrationRun	001		Mon Nov 17 22:27:07 CET 2014	Unknown
Noise file from run 001 PedestalRun_001 FIRRun_001 At room temperature See DelayRun_001
19	Mon Nov 17 22:28:09 2014	Hao Yin		CalibrationRun	001		Mon Nov 17 22:27:07 CET 2014	Unknown
Noise file from run 001 PedestalRun_001 FIRRun_001 At room temperature See DelayRun_001
20	Mon Nov 17 23:04:57 2014	Hao Yin	Belle SVD	PedestalRun_002		10338	Mon Nov 17 23:03:03 CET 2014	Unknown
Pedestal run at room temperature. 6 subevents. Noise reference run. Delay as latest run. Reference run for bad strips.
21	Tue Nov 18 01:03:18 2014	Hao Yin	Belle SVD	Remapped FADC inputs			Tue Nov 18 01:03:32 CET 2014	Unknown
We moved the second cable to the third connector on the FADC to match DESY testbeam conditions.
22	Tue Nov 18 01:05:04 2014	Hao Yin	Belle SVD	PedestalRun_003			Tue Nov 18 01:03:32 CET 2014	Unknown
New pedestal run after switching the connectors. At room temperature
23	Tue Nov 18 09:45:59 2014	Hao Yin		FIRRun_002	002		Tue Nov 18 09:45:58 CET 2014	Unknown
New FIR run after reconecting to original setting.
24	Tue Nov 18 09:48:53 2014	Hao Yin	Belle SVD	PedestalRun_004		10000	Tue Nov 18 09:48:30 CET 2014	Unknown
At room temperature. Old delay settings and FIRRun_002
25	Tue Nov 18 09:51:11 2014	Hao Yin		CalibrationRun_002			Tue Nov 18 09:50:24 CET 2014	Unknown
At room temperature PedestalRun004 Latest delay settings and FIRRun
26	Tue Nov 18 10:12:25 2014	Hao Yin	Belle SVD	6let PedestalRun_005		10000	Tue Nov 18 10:11:45 CET 2014	Unknown
At room temperature Latest delay, FIRRun002. Check for bad strips.
27	Tue Nov 18 10:26:56 2014	Hao Yin	Belle SVD	CalibrationRun_003			Tue Nov 18 10:26:52 CET 2014	Unknown
At room temperature Latest delay and FIRRun
32	Tue Nov 18 18:45:01 2014	Hao Yin	Belle SVD	Trigger Delay scan			Tue Nov 18 18:21:50 CET 2014	Unknown
At room temperature First run was at: 23 (no track) TimingRun_001: Trigger delay: 26 TimingRun_002: Trigger delay: 29 TimingRun_003: Trigger delay: 32 TimingRun_004: Trigger delay: 20 TimingRun_005: Trigger delay: 17 TimingRun_005: Trigger delay: 14 Trigger chip delay: 110
33	Tue Nov 18 20:26:12 2014	Hao Yin	Belle SVD	HardwareRun_001			Tue Nov 18 18:21:50 CET 2014	Unknown
At room temperature Latest ADC scan and FIR run. Latest CAL. Position: 0.0, see elog entry.
42	Wed Nov 19 20:04:53 2014	Hao Yin	Belle SVD	PedestalRun_006				Unknown
Temperature: See attachment FIRFilterRun_002 Layer 3-n side deactivated, because Hao broke it.
43	Wed Nov 19 20:07:05 2014	Hao Yin	Belle SVD	HardwareRun_002				Unknown
Multi-6 cooled. See latest Noise, and PedestalRun.
46	Wed Nov 19 22:25:29 2014	Hao Yin	Belle SVD	PedestalRun_008 [CheckLayout]				Unknown
cooled (temperature see attachment latest noise run), latest Noise, FIR settings with the right layout mapping.

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