# 40 mhz
# single peak mode (1 sample)
# 50ns peaking time
# 30ns trigger window (built from 5ns window, thus ~12.5ns later)
# NECO
#
# Data processing with FADC+PROC
# SPS Testbeam - full setup
# FADC 0 four hybrids
# FADC 1 four hybrids
#
#
# CI 07 may 2008
#
#
# Lines preceded by a # or ; sign are ignored.
#
# [rem] comments a whole section until the next section start marked by [xxx] .
#
# [vme]
# VME addresses are given in the format
# {module_name} = {vme_module_number},{vme_address_hex}
# nec ... NECO module
# adf ... particular FADC module
#
# Please note that the address ranges are not defined here,
# they are implicitly given by the hardware.
# Module numbers must fill from 0 (this is not checked).
# Please note that no range checking is performed.
# There is no access to VME modules that are not included in this list,
[vme]
nec = 0,0x1a000000
adf = 0,0x1b000000
adf = 1,0x2b000000
# [nec]
# NECO related information
# mod = 0|1,{shift_register_delay},{adc_range},{win_delay},{win_length},{dead_time},{time_lat},{max_trg}
# (default: 0,75,0,50?,900?,36,2,1)
# res = {list of entries in reset sequence} (default: 2,4)
# cal = {list of entries in cal sequence} (default: 2,3,250,251)
# sw5 = {list of entries in single cal sequence} (default: 2,3)
# str = {list of entries in software trigger sequence} (default: 75)
# htr = {list of entries in hardware trigger sequence} (default: 74)
#
# mod specifies to use either the sequencer (0) or the shift register (1) for hardware trigger and the
# delay of the shift register (0..255); adc_range (0=1Vpp, 1=2Vpp) -- ignored; win_delay and win_length define
# the starting point (relative to the APV trigger) and length of the ADC gate in transparent mode; dead_time is
# the number of 254MHz clock cycles which are set to zero for time measurement after an incoming trigger;
# time_lat is the latency for time measurement in terms of 40MHz clock cycles; max_trg is the number of incoming
# triggers which required to activate the veto logic (usually 1; 0 completely disables the veto logic)
# res, cal, sw5, str and htr are containing the bits to set in the 256-element sequencer memory (nothing is set at -1)
# Please note that cal+str together produce a calibration request plus subsequent normal trigger, so the time
# between them is the latency. sw5 is used to send a single cal request to achieve the correct polarity in
# case the APV inverter is turned on (this feature only works for entire MAMBOs halves = groups of 3 REBOs)
#
# These settings are quite fragile! Do not modify until you know exactly what you are doing.
[nec]
# 30m cables, 40mhz, Tp=50ns, single-trigger
#mod = 0,75,0,70,250,36,2,1
#htr = 61,-1,-1,-1,-1,-1,-1,-1
#str = 100,-1,-1,-1,-1,-1,-1,-1
# TESTBEAM Nov 07, 30m cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 59,62,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1
# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, single-trigger (1 samples)
mod = 0,75,0,70,250,36,2,1
htr = 63,-1,-1,-1,-1,-1,-1,-1
str = 100,-1,-1,-1,-1,-1,-1,-1
# SiLC TESTBEAM June 08, 7m sc cables, 30m repeater cables, 40mhz, Tp=50ns, multi-trigger (6 samples)
#mod = 0,75,0,70,950,36,2,1
#htr = 61,64,-1,-1,-1,-1,-1,-1
#str = 100,103,-1,-1,-1,-1,-1,-1
#common settings
res = 2, 4, -1, -1,-1,-1,-1,-1
cal = 2, 3,250,251,-1,-1,-1,-1
sw5 = 2, 3, -1, -1,-1,-1,-1,-1
# [daq]
# DAQ related specifications are given in the format
# ads = {N},{search_max_subevents},0,x
# ini = {initevents},{readout_mode},0,x
# deh = {module_position},{apv_position},0,x
# i2t = {N},0,0,x
# pat = 0,0,0,{data_file_path}
# clk = {N},{Delay25 frequency range},0,x
# pdl = {Trigger input delay},0,0,x
# crd = {crate_number},{clkdel},{trgdel},x
#
# ads N gives the number of samples that are read out from the FIFO1 in transparent mode, search_max_subevents is the
# maximum number of subevents to search for within one ADC stream (default=1).
# ini: initevents is the number of software triggers in the beginning of a run for pedestal and noise
# evaluation. At the beginning of each run, 2*initevents are generated by software, after that the
# selected trigger source (hardware, software of calibration) is activated. The initial evaluation
# events are written to disk as normal events are.
# ini: readout_mode defines whether events beyond the initevents are read in raw transparent mode from FIFO1 (0) or
# in processed mode (1) where only hit information is read from FIFO3
# deh is the APV chip for which single strip histograms are recorded
# i2t is the maximum number of I2C retries in case of failure
# pat specifies the save path for data files (must include a trailing backslash!)
# clk gives the system clock period in integer ns (25 max.) and the frequency range for the Delay25 chip:
# 0...40 MHz, 1...80 MHz, 2...32 MHz, 3...64 MHz
# pdl specifies the delay setting for the trigger input in 0.5ns steps (0..49)
# crd define the global clock and trigger delays between NECO and SVD3_buffer for crates 0 and 1
# NOTE: clock and trigger is NOT propagated to any crate(s) NOT specified here
[daq]
# TESTBEAM Nov 07
#Standard
ads = 250,1,0,x
# TESTBEAM Nov 07
#Multitrigger (6)
#ads = 950,6,0,x
# RAW (transparent mode) readout
ini = 300,0,0,x
# PROCESSED readout
#ini = 300,1,0,x
deh = 1,0,0,x
i2t = 5,0,0,x
pat = 0,0,0,F:\\testbeam\\cern_jun08\\silc\\data\\
#standard 40mhz clock (25ns)
clk = 25,0,0,x
pdl = 25,0,0,x
#crate distribution delays (set to mid-range to allow adjustments in both directions)
crd = 0,25,25,x
#we don't use crate 1, so we don't set any delay here -> no clock/trigger to crate 1
###crd = 1,25,25,x
# [hit]
# Hit recognition variables are specified here
# hcs = {hitcut_seed_strip},{hitcut_neighbor_strips}
# nok = {x.x},0
#
#
# hcs gives seed and neighbor hit cuts in units of strip sigma
# nok states the threshold over average noise at which strips are excluded from further analysis (to exclude noisy strips)
[hit]
# si sensor
hcs = 4.0,4.0
# do not exclude strips
nok = 2000.0,0
# [cal]
# Calibration related data
# lvl = {level},0
# lat = {latbeg},{latend}
# sam = {average_samples},{number of samples in 6-tuple mode}
# grp = {number_of_groups},0
# lg6 = {latency},{group}
# lv6 = {startlevel},{endlevel}
#
# lvl is the CLVL amplitude (0..255), 1 is 625e-, 36 is 1 MIP (22500e-) nominally, in reality 26 is 1 MIP
# lat is the Latency range to cover (latend-latbeg>=2, latend-latbeg<=15)
# sam is the number of samples to average per position for normal and 6-tuple modes
# grp is how many groups to scan (<=8), first group is strips 0,8,16,..., second group is 1,9,17,..., ...
# lg6 defines the latency in 6-tuple mode and which group to observe in that mode
# lv6 defines the scan range of amplitude in 6-tuple mode
[cal]
#real 1 MIP level (22400e)
lvl = 26,0
#real 5 MIPs level
#lvl = 130,0
#LAT=95/98 Calibration (short display)
#lat = 89,100
#LAT=95/98 Calibration (short display for >=50mhz)
#lat = 81,98
#LAT=95/98 Calibration (long peak mode tail display)
lat = 75,100
#common settings
sam = 50,150
grp = 8,0
#6-tuple mode settings
lg6 = 97, 1
#lv6 = 1,95
lv6 = 50,52
# [i2c]
# This section defines one or more I2C sets for the APV25. In the [mod] section, those sets are referenced to by their number.
# ia2 = {number},{mode},{lat},{ipre},{ipcasc},{ipsf},{isha},{issf},{ipsp},{imuxin},{vfp},{vfs},{vpsp},{muxgain}
#
# The I2C settings must be individually numbered (ascending from 0). The easiest case is to use the same
# settings for all chips of one type, but one could go so far to use separate settings for each chip.
# vadj/vpsp is set individually for each apv in the [mod] section, the value specified here is meaningless.
[i2c]
# apv25s1, peak, inverter ON, Tp=50ns, (p side)
ia2 = 0, 63, 95, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, peak, inverter OFF, Tp=50ns, (n side)
ia2 = 1, 31, 95, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, multi-peak, inverter ON, Tp=50ns, (p side)
#ia2 = 0, 61, 95, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# apv25s1, multi-peak, inverter OFF, Tp=50ns, (n side)
#ia2 = 1, 29, 95, 98, 52, 34, 34, 34, 55, 34, 30, 60, 0, 4
# [mod]
# Detector module (actually hybrid) specifications are given in the format
# mod = {module_position},{crate_number},{mambo_number},{rebo_number},{hybrid_number},m,{AD8128_peak},{rebo_clkdelay},{rebo_trgdelay},0,0,0,0,{Name}
# apv = {module_position},{apv_position},{i2c_address},{i2c_settings},{vadj/vpsp},x,0,0,{fadc_offset},{fadc_number},{fadc_channel},{fadc_clkdelay [0..49]},{AD8128_gain},x
#
# mod gives the hybrid/module properties: The position counts from 0 to 7 in beam direction,
# Name must not contain blanks ("_" is allowed).
# apv describes the chips located on a hybrid
# and the ADC channel where they are read out, either a Vienna ADC (a) or a FED (f).
# The ADC offset is only available with the Vienna ADCs and shifts the baseline.
# The individual chip vadj setting dominates over the [i2c] setting.
[mod]
# module 0
mod = 0,0,0,2,0,m,45,25,0,0,0,0,0, 0_SiLC_05/05
apv = 0,0,36,0,30,x,0,0,5,0,1,12,100,x
apv = 0,1,38,0,30,x,0,0,5,0,2,15,100,x
# module 1
mod = 1,0,0,2,1,m,45,25,0,0,0,0,0, 1_SiLC_07/07
apv = 1,0,36,0,30,x,0,0,5,0,5,15,100,x
apv = 1,1,38,0,30,x,0,0,5,0,6,16,100,x
# module 2
mod = 2,0,0,2,2,m,45,25,0,0,0,0,0, 2_SiLC_06/03
apv = 2,0,36,0,30,x,0,0,5,0,9,10,100,x
apv = 2,1,38,0,30,x,0,0,5,0,10,15,100,x
# module 3
mod = 3,0,0,2,3,m,45,25,0,0,0,0,0, 3_SiLC_04/04
apv = 3,0,36,0,30,x,0,0,5,0,13,12,100,x
apv = 3,1,38,0,30,x,0,0,5,0,14,14,100,x
# module 4
mod = 4,0,1,1,0,m,45,25,0,0,0,0,0, 4_SiLC_03/10
apv = 4,0,36,0,30,x,0,0,110,1,1,14,100,x
apv = 4,1,38,0,30,x,0,0,110,1,2,15,100,x
# module 5
mod = 5,0,1,1,1,m,45,25,0,0,0,0,0, 5_SiLC_12/08
apv = 5,0,36,0,30,x,0,0,110,1,5,14,100,x
apv = 5,1,38,0,30,x,0,0,110,1,6,16,100,x
# module 6
mod = 6,0,1,1,2,m,45,25,0,0,0,0,0, 6_SiLC_10/02
apv = 6,0,36,0,30,x,0,0,110,1,9,12,100,x
apv = 6,1,38,0,30,x,0,0,120,1,10,15,100,x
# module 7
mod = 7,0,1,1,3,m,45,25,0,0,0,0,0, 7_SiLC_20/09
apv = 7,0,36,0,30,x,0,0,125,1,13,10,100,x
apv = 7,1,38,0,30,x,0,0,115,1,14,14,100,x
# [bad]
# Bad channels description table
# bad = {module_position},{apv_position},{List of 18 strip values or -1}
#
# Maps bad channels, which are then excluded from hit search. Up to 18 bad strips can be entered per line,
# more lines per APV are allowed. Unused values in the list must be filled with -1
[bad]
#bad = 2,0,73,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1
[sen]
# sensor configuration
# sen = {sensor number},{number strips on p side},{numeration direction p},{number strips on n side},{numeration direction n},{first_full},{last_full},{pitch p [µm]}, {pitch n [µm]},{angle [°]},{height [µm]}
# apv = {sensor number},{module_position},{apv_position},{first_strip},{num_floating},{side},0,0,0,0,0
... 193 more lines ...
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