Home CMS Production Clean room MedAustron HEPHY testbeams old

electronics module assembly SiDDaTA scratch

HEPHY logbook of the Electronics Group, Page 1 of 4  Not logged in

Find |  Select |  Login |  Help

Full | Summary | Threaded     -- All entries -- Last day Last 3 Days Last week Last month Last 3 Months Last 6 Months Last Year -- Type -- Common Measurement -- Project -- SPS Testbeam June08 Belle II PixelFED -- Measurement Type -- hybrid module source system  64 Entries

Goto page 1, 2, 3, 4   Next  All

ID Date Author Project Measurement Type Object ID Subject Text   67   Mon Nov 30 22:35:41 2015 Hao Yin Belle II system Hardware_Room_With_Cold_I2C   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 ADC shifted by 9 (4.5ns) all sensors      65   Mon Nov 30 20:27:42 2015 Hao Yin Belle II system Hardware_Room_With_Cold_I2C   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 ADC shifted by 5 (2.5ns) all sensors      64   Mon Nov 30 20:16:37 2015 Hao Yin Belle II system Hardware_Room_With_Cold_I2C   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 ADC delay shifted by 3 (1.5ns)      63   Mon Nov 30 20:06:15 2015 Hao Yin Belle II system Hardware_Room_With_Cold_I2C   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 with room temp i2c config      62   Mon Nov 30 19:48:05 2015 Hao Yin Belle II system Hardware_Room_With_Cold_I2C   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 with room temp i2c config      61   Mon Nov 30 19:01:54 2015 Hao Yin Belle II system Hardware_Cold   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 Temp = 0°C      60   Mon Nov 30 18:49:23 2015 Hao Yin Belle II system Hardware_Cold   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001 target: -Z      59   Mon Nov 30 18:45:49 2015 Hao Yin Belle II system PedestalRun_Cold   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001        58   Mon Nov 30 18:44:04 2015 Hao Yin Belle II system FIRRun_Cold   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns)        57   Mon Nov 30 18:32:13 2015 Hao Yin Belle II system ADC Delay Scan Cold   ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns)      56   Mon Nov 30 17:47:54 2015 Hao Yin Belle II system HardwareRun002   ADC Hot, FIRRun001, PedestalRun001 target: -Z room temp pedrun      55   Mon Nov 30 17:23:51 2015 Hao Yin Belle II system HardwareRun001   ADC Hot, FIRRun001, PedestalRun001 room temp pedrun target: BW      54   Mon Nov 30 17:13:47 2015 Hao Yin Belle II system PedestalRun   ADC Hot, FIRRun001 room temp pedrun      53   Mon Nov 30 17:11:17 2015 Hao Yin Belle II module FIRRun001 FIRRun001 aft ADC_HOT FirRun 20 min after I2C      52   Mon Nov 30 15:18:12 2015 Hao Yin Belle II module ADC_DELAY_HOT ADC delay hot ADC delay scan at room temp and 20 min after APV I2C config. measured values at display in the      51   Mon Nov 30 15:12:19 2015 Hao Yin       FIR_ADC config FIR filter and ADC delay test: ADC delay and FIR filter with and without cooling to reproduce error detected        50   Fri May 29 11:47:56 2015 Hao Yin Belle II system PS Filter Testing PS LV filter and quantifying the required min noise lvl Data of this entry is recorded in the folder: LV315kHz_Injections Injecting noise to LV with a freq.      49   Wed May 27 09:30:54 2015 Hao Yin Belle II system CAEN PS Primary side   Measured Primary side of caen wo load (setup attachment 2 and prelimilary res. attachment 1. )      48   Mon May 25 20:27:23 2015 Hao Yin Belle II system Caen PS base line measurements   Baseline noise measurements wo injection. measure noise in both HV and LV. wings of APV25 using cmc with 128      47   Mon May 25 10:38:03 2015 Hao Yin Belle II system L5 Ladder Emission Test Emission (TestNr: 16) base line noise measurement are saved in SYSTEM_CHECK_AFTER_WE.

Goto page 1, 2, 3, 4   Next  All

ELOG V3.1.5-fc6679b