general: # General configuration
  readout_system: # Readout system, available platforms are BDAQ53 or MIO3 (+ GPAC). BDAQ53 is default
  output_directory: /home/silicon/Data/2024_03_MAUS/TJ-Monopix2/h5  #'/media/raid/data/tjmonopix2/2021-10-25_elsa/tuning' # Top-level output data directory, default is the current folder where the script is started

# Connected Modules
modules:
  module_0: # Arbitrary name of module, defines folder name with chip sub folders
    identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
    chip_0: # Arbitrary name of chip, defines folder name with chip data
      chip_sn: "W02R01"
      chip_id: 0
      receiver: "rx0"
      chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W02R01/20240222_174415_threshold_scan_interpreted.h5 # If defined: use config from in file (either .cfg.yaml or .h5). If not defined use chip config of latest scan and std. config if no previous scan exists
      record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
      use_good_pixels_diff: False
      send_data: "tcp://127.0.0.1:5500" # Socket address of online monitor
      disable_columns: []
  module_1: # Arbitrary name of module, defines folder name with chip sub folders
    identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
    chip_1: # Arbitrary name of chip, defines folder name with chip data
      chip_sn: "W08R19"
      chip_id: 1
      receiver: "rx2"
      chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W08R19/20230708_095321_threshold_scan_interpreted.h5 # If defined: use config from in file (either .cfg.yaml or .h5). If not defined use chip config of latest scan and std. config if no previous scan exists
      record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
      use_good_pixels_diff: False
      send_data: "tcp://127.0.0.1:5501" # Socket address of online monitor
      disable_columns: []


TLU:
  TRIGGER_MODE: 3 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3)
  TRIGGER_SELECT: 0 # Selecting trigger input: HitOr (individual, TDC loop-through) (16), RX1 (multi purpose) (8), RX0 (TDC loop-trough) (4), HitOR [DP_ML_5 and mDP] (logical OR of all eight lines) (3), HitOR [mDP only] (logical OR of all four lines) (2), HitOR [DP_ML_5 only] (logical OR of all four lines) (1), disabled (0)
  TRIGGER_INVERT: 0 # Inverting trigger input: HitOr (individual, TDC loop-through) (16), RX1 (multi purpose) (8), RX0 (TDC loop-trough) (4), HitOR [DP_ML_5 and mDP] (logical OR of all eight lines) (3), HitOR [mDP only] (logical OR of all four lines) (2), HitOR [DP_ML_5 only] (logical OR of all four lines) (1), disabled (0)
  TRIGGER_LOW_TIMEOUT: 0 # Maximum wait cycles for TLU trigger low.
  TRIGGER_VETO_SELECT: 0 # Selecting trigger veto: AZ VETO (2), RX FIFO full (1), disabled (0). Set to (2) if SYNC FE is enabled.
  TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES: 5 # TLU trigger minimum length in TLU clock cycles
  DATA_FORMAT: 0 # Select trigger data format: only trigger number (0), only time stamp (1), combined, 15 bit time stamp + 16 bit trigger number (2)
  EN_TLU_VETO: 0 # Assert TLU veto when external veto. Activate this in order to VETO triggers if SYNC FE is enabled.
  TRIGGER_DATA_DELAY: 8 # Depends on the cable length and should be adjusted (run scan/tune_tlu.py)

TDC:
  EN_WRITE_TIMESTAMP: 1 # Writing trigger timestamp
  EN_TRIGGER_DIST: 1 # Measuring trigger to TDC delay with 640MHz clock
  EN_NO_WRITE_TRIG_ERR: 1 # Writing TDC word only if valid trigger occurred
  EN_INVERT_TDC: 0 # Inverting TDC input
  EN_INVERT_TRIGGER: 0 # Inverting trigger input, e.g. for using Test output from EUDET TLU

hardware: # Setup-specific hardware settings
  enable_NTC: True # Only enable if you know you have the correct resistors mounted on the BDAQ board!

electron_conversion: # Charge conversion from DAC to e⁻, typically 8.8 for DC and 13.3 for AC (slightly chip dependent!)
  DC_coupled: 8.8
  AC_coupled: 13.3
calibration: # Setup-specific calibration constants
  bdaq_ntc: # Resistors on BDAQ board for NTC readout
    R16: 1.2e6
    R17: 20e3
    R19: 7.95e3

# Standard analysis settings
# Scans might overwrite these settings if needed.
# Detailed description of parameters in bdaq53/analysis/analysis.py
analysis:
  skip: False # Omit analysis in scans
  create_pdf: True # Create analysis summary pdf
  # module_plotting: True  # Create combined plots for chip in a module
  store_hits: True # store hit table
  cluster_hits: False # store cluster data
  # analyze_tdc: False # analyze TDC words
  # use_tdc_trigger_dist: False # analyze TDC to TRG distance
  # align_method: 0 # how to detect new events
  # chunk_size: 1000000 # scales amount of data in RAM (~150 MB)
  # blocking: True # block main process during analysis