# example config file: Ex0.conf
[RunControl]
#pCT_STOP_RUN_AFTER_N_SECONDS = 3000000
# from the base RunControl.cc
#EUDAQ_CTRL_PRODUCER_LAST_START = my_pd0
#EUDAQ_CTRL_PRODUCER_FIRST_STOP = my_pd0
# Steer which values to display in the GUI: producerName and displayed value are seperated by a ",". 
ADDITIONAL_DISPLAY_NUMBERS = "log,_SERVER"


[Producer.aida_tlu]
## GENERAL PARAMETERS
verbose= 1
skipconf= 0
confid= 20201311
delayStart= 200  

## HDMI CONFIGURATION
#  4-bits to determine direction of HDMI pins
HDMI1_set= 0x7 #1= output (driven by TLU), 0 = input. bit 0=CONT, 1=SPARE, 2=TRIG, 3=BUSY for eudet, Busy needs to be 0. (0b0111 = 0x7)
HDMI2_set= 0x7
HDMI3_set= 0x7
HDMI4_set= 0x7
#  Clock source (0= no clock, 1= Si5345, 2= FPGA)
HDMI1_clk = 0
HDMI2_clk = 0
HDMI3_clk = 0
HDMI4_clk = 0
#  Enable/Disable clock on differential LEMO
LEMOclk = 0

## PMT POWER CONFIGURATION
PMT1_V= 0.8 #0.6363 #Szinti 4x4cm
PMT2_V= 0.8 #0.6363 #Szinti 4x4cm
PMT3_V= 0.0
PMT4_V= 0.0

## TRIGGER CONFIGURATION
trigMaskHi = 0x00000000
trigMaskLo = 0x00000008 #0x00000008 #0x00010002 #0x00000001  #8 coinc1+2
in0_STR = 0	# 0 
in0_DEL = 0	# 18
in1_STR = 0	# 0
in1_DEL = 0	# 18
in2_STR = 0	# 0
in2_DEL = 0 	# 0
in3_STR = 0
in3_DEL = 0
in4_STR = 0
in4_DEL = 0
in5_STR = 0 #streches pulse from 6.25ns (at 0) to 12.5ns
in5_DEL = 0
# Generate internal triggers (in Hz, 0= no triggers)
InternalTriggerFreq= 0 #4000 #00

## DISCRIMINATOR THRESHOLDS
DACThreshold0 = -0.025 #-0.025 #-0.012
DACThreshold1 = -0.012 #-0.025 #-0.012
DACThreshold2 = -0.012
DACThreshold3 = -0.12
DACThreshold4 = -0.12 #-0.0066
DACThreshold5 = -0.12

## DUT CONFIGURATION
 # DUTMask Which DUTs are on
#DUTMask= 0x3 #6 bit 0= DUT1, bit 1= DUT2, bit 2= DUT3, bit 3= DUT4
DUTMask= 0xA

 # DUTMaskMode Define AIDA (11) or EUDET (00) mode (2 bits per DUT)
DUTMaskMode= 0x00 #0x00

 # In EUDET mode: 0 = standard trigger/busy mode, 1 = raising BUSY outside handshake vetoes triggers (2 bits per DUT, 0x3= DUT 4! -backwards!)
DUTMaskModeModifier= 0x30 #0x30 #0xC0 PS: Check what this does! 0x0 würde ich hier eingeben

 # Ignore the BUSY signal for a DUT (0xF)
DUTIgnoreBusy= 0x0 #ignores triggers
DUTIgnoreShutterVeto= 0x0
EnableRecordData = 1


# EnableShutterMode: 0x0. If 1, shutter mode is enabled. If 0, shutter mode is disabled.
EnableShutterMode= 0x0
# Define which input is used for shutter source [0 - 5]
ShutterSource = 5
# 32-bit counter of clocks. Set to 0 to not use internal shutter generator.
InternalShutterInterval = 0
# 32-bit counter of clocks
ShutterOnTime = 0 #start of shutter after trigger
# 32-bit counter of clocks
ShutterVetoOffTime = 0 #time after input-trigger, until first trigger is sent to output
# 32-bit counter of clocks
ShutterOffTime = 200000000 #end of shutter after trigger #200000000 = 5s (multiples of 25ns)

## DATA COLLECTOR
EUDAQ_DC= tlu_dc

## TLU MONITOR PARAMETER
FileComment="mpw3"
PlotWindowSizeinns=40e9
MinSpillTimeOnins=4.5
MinSpilldownTimeins=0.5
ThreshEvBegin=1
ThreshEvEnd=1
ThreshPartBegin=1
ThreshPartEnd=1




[LogCollector.log]
# Currently, all LogCollectors have a hardcoded runtime name: log
# nothing


[DataCollector.tlu_dc]
EUDAQ_FW=native
# the format of data file
EUDAQ_FW_PATTERN= /home/silicon/Data/2024_03_MAUS/TLU/tlu_run$6R$X
# the name pattern of data file
# the $12D will be converted a data/time string with 12 digits.
# the $6R will be converted a run number string with 6 digits.
# the $X will be converted the suffix name of data file.
DISABLE_PRINT = 1


[Producer.tjmonopix2_AB]
# connection to the data collector
EUDAQ_DC = dc_tjmonopix2_AB
ENABLE_BDAQ_RECORD = 1
ENABLE_HITOR = 1

START_ROW = 0
STOP_ROW = 512
START_COLUMN = 448
STOP_COLUMN = 512
WAIT_FOR_FPGA = 1

[DataCollector.dc_tjmonopix2_AB]
EUDAQ_FW = native
EUDAQ_FW_PATTERN = /home/silicon/Data/2024_03_MAUS/TJ-Monopix2/raw/run$3R_tjmonopix2_AB_$12D$X
DISABLE_PRINT = 1


[Producer.tjmonopix2_CD]
# connection to the data collector
EUDAQ_DC = dc_tjmonopix2_CD
ENABLE_BDAQ_RECORD = 1
ENABLE_HITOR = 1

START_ROW = 0
STOP_ROW = 512
START_COLUMN = 448
STOP_COLUMN = 512
WAIT_FOR_FPGA = 1


[DataCollector.dc_tjmonopix2_CD]
EUDAQ_MN = monopix2_mon
EUDAQ_DATACOL_SEND_MONITOR_FRACTION = 1000
EUDAQ_FW = native
EUDAQ_FW_PATTERN = /home/silicon/Data/2024_03_MAUS/TJ-Monopix2/raw/run$3R_tjmonopix2_CD_$12D$X
DISABLE_PRINT = 1



[Producer.elog1]
#start_cmd = "./get_mpw4_configs.sh" # command (shell script) to execute before starting a run
#files2log = "peary_config.cfg, matrix_mpw4.txt" #files to attach to the auto Elog entries, EUDAQ config will be logged by default

general: # General configuration
  readout_system: # Readout system, available platforms are BDAQ53 or MIO3 (+ GPAC). BDAQ53 is default
  output_directory: /home/silicon/Data/2024_03_MAUS/TJ-Monopix2/h5  #'/media/raid/data/tjmonopix2/2021-10-25_elsa/tuning' # Top-level output data directory, default is the current folder where the script is started

# Connected Modules
modules:
  module_0: # Arbitrary name of module, defines folder name with chip sub folders
    identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
    chip_0: # Arbitrary name of chip, defines folder name with chip data
      chip_sn: "W02R01"
      chip_id: 0
      receiver: "rx0"
      chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W02R01/20240222_174415_threshold_scan_interpreted.h5 # If defined: use config from in file (either .cfg.yaml or .h5). If not defined use chip config of latest scan and std. config if no previous scan exists
      record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
      use_good_pixels_diff: False
      send_data: "tcp://127.0.0.1:5500" # Socket address of online monitor
      disable_columns: []
  module_1: # Arbitrary name of module, defines folder name with chip sub folders
    identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
    chip_1: # Arbitrary name of chip, defines folder name with chip data
      chip_sn: "W08R19"
      chip_id: 1
      receiver: "rx2"
      chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W08R19/20230708_095321_threshold_scan_interpreted.h5 # If defined: use config from in file (either .cfg.yaml or .h5). If not defined use chip config of latest scan and std. config if no previous scan exists
      record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
      use_good_pixels_diff: False
      send_data: "tcp://127.0.0.1:5501" # Socket address of online monitor
      disable_columns: []


TLU:
  TRIGGER_MODE: 3 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3)
  TRIGGER_SELECT: 0 # Selecting trigger input: HitOr (individual, TDC loop-through) (16), RX1 (multi purpose) (8), RX0 (TDC loop-trough) (4), HitOR [DP_ML_5 and mDP] (logical OR of all eight lines) (3), HitOR [mDP only] (logical OR of all four lines) (2), HitOR [DP_ML_5 only] (logical OR of all four lines) (1), disabled (0)
  TRIGGER_INVERT: 0 # Inverting trigger input: HitOr (individual, TDC loop-through) (16), RX1 (multi purpose) (8), RX0 (TDC loop-trough) (4), HitOR [DP_ML_5 and mDP] (logical OR of all eight lines) (3), HitOR [mDP only] (logical OR of all four lines) (2), HitOR [DP_ML_5 only] (logical OR of all four lines) (1), disabled (0)
  TRIGGER_LOW_TIMEOUT: 0 # Maximum wait cycles for TLU trigger low.
  TRIGGER_VETO_SELECT: 0 # Selecting trigger veto: AZ VETO (2), RX FIFO full (1), disabled (0). Set to (2) if SYNC FE is enabled.
  TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES: 5 # TLU trigger minimum length in TLU clock cycles
  DATA_FORMAT: 0 # Select trigger data format: only trigger number (0), only time stamp (1), combined, 15 bit time stamp + 16 bit trigger number (2)
  EN_TLU_VETO: 0 # Assert TLU veto when external veto. Activate this in order to VETO triggers if SYNC FE is enabled.
  TRIGGER_DATA_DELAY: 8 # Depends on the cable length and should be adjusted (run scan/tune_tlu.py)

TDC:
  EN_WRITE_TIMESTAMP: 1 # Writing trigger timestamp
  EN_TRIGGER_DIST: 1 # Measuring trigger to TDC delay with 640MHz clock
  EN_NO_WRITE_TRIG_ERR: 1 # Writing TDC word only if valid trigger occurred
  EN_INVERT_TDC: 0 # Inverting TDC input
  EN_INVERT_TRIGGER: 0 # Inverting trigger input, e.g. for using Test output from EUDET TLU

hardware: # Setup-specific hardware settings
  enable_NTC: True # Only enable if you know you have the correct resistors mounted on the BDAQ board!

electron_conversion: # Charge conversion from DAC to e⁻, typically 8.8 for DC and 13.3 for AC (slightly chip dependent!)
  DC_coupled: 8.8
  AC_coupled: 13.3
calibration: # Setup-specific calibration constants
  bdaq_ntc: # Resistors on BDAQ board for NTC readout
    R16: 1.2e6
    R17: 20e3
    R19: 7.95e3

# Standard analysis settings
# Scans might overwrite these settings if needed.
# Detailed description of parameters in bdaq53/analysis/analysis.py
analysis:
  skip: False # Omit analysis in scans
  create_pdf: True # Create analysis summary pdf
  # module_plotting: True  # Create combined plots for chip in a module
  store_hits: True # store hit table
  cluster_hits: False # store cluster data
  # analyze_tdc: False # analyze TDC words
  # use_tdc_trigger_dist: False # analyze TDC to TRG distance
  # align_method: 0 # how to detect new events
  # chunk_size: 1000000 # scales amount of data in RAM (~150 MB)
  # blocking: True # block main process during analysis

general: # General configuration
  readout_system: # Readout system, available platforms are BDAQ53 or MIO3 (+ GPAC). BDAQ53 is default
  output_directory: /home/silicon/Data/2024_03_MAUS/TJ-Monopix2/h5  #'/media/raid/data/tjmonopix2/2021-10-25_elsa/tuning' # Top-level output data directory, default is the current folder where the script is started

# Connected Modules
modules:
  module_2: # Arbitrary name of module, defines folder name with chip sub folders
    identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
    chip_2: # Arbitrary name of chip, defines folder name with chip data
      chip_sn: "W14R18"
      chip_id: 2
      receiver: "rx2"
      chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W14R18/20240329_175240_threshold_scan_interpreted.h5
      record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
      use_good_pixels_diff: False
      send_data: "tcp://127.0.0.1:5502" # Socket address of online monitor
      disable_columns: [484, 485]
  module_3: # Arbitrary name of module, defines folder name with chip sub folders
    identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
    chip_3: # Arbitrary name of chip, defines folder name with chip data
      chip_sn: "W18R03"
      chip_id: 3
      receiver: "rx3"
      chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W18R03/20240222_183330_threshold_scan_interpreted.h5 # If defined: use config from in file (either .cfg.yaml or .h5). If not defined use chip config of latest scan and std. config if no previous scan exists
      record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
      use_good_pixels_diff: False
      send_data: "tcp://127.0.0.1:5503" # Socket address of online monitor
      disable_columns: [456, 457]
  # module_3: # Arbitrary name of module, defines folder name with chip sub folders
  #   identifier: "unknown" # Module/wafer/PCB identifier, has to be given (e.g. SCC number)
  #   chip_3: # Arbitrary name of chip, defines folder name with chip data
  #     chip_sn: "W08R03"
  #     chip_id: 3
  #     receiver: "rx3"
  #     chip_config_file: /home/silicon/TJ-Monopix2/2024_03_MAUS_Tuning/W08R03/20240222_151416_threshold_scan_interpreted.h5 # If defined: use config from in file (either .cfg.yaml or .h5). If not defined use chip config of latest scan and std. config if no previous scan exists
  #     record_chip_status: True # Add chip statuses to the output files after the scan (link errors and powering infos)
  #     use_good_pixels_diff: False
  #     send_data: "tcp://127.0.0.1:5503" # Socket address of online monitor
  #     disable_columns: []


TLU:
  TRIGGER_MODE: 3 # Selecting trigger mode: Use trigger inputs/trigger select (0), TLU no handshake (1), TLU simple handshake (2), TLU data handshake (3)
  TRIGGER_SELECT: 0 # Selecting trigger input: HitOr (individual, TDC loop-through) (16), RX1 (multi purpose) (8), RX0 (TDC loop-trough) (4), HitOR [DP_ML_5 and mDP] (logical OR of all eight lines) (3), HitOR [mDP only] (logical OR of all four lines) (2), HitOR [DP_ML_5 only] (logical OR of all four lines) (1), disabled (0)
  TRIGGER_INVERT: 0 # Inverting trigger input: HitOr (individual, TDC loop-through) (16), RX1 (multi purpose) (8), RX0 (TDC loop-trough) (4), HitOR [DP_ML_5 and mDP] (logical OR of all eight lines) (3), HitOR [mDP only] (logical OR of all four lines) (2), HitOR [DP_ML_5 only] (logical OR of all four lines) (1), disabled (0)
  TRIGGER_LOW_TIMEOUT: 0 # Maximum wait cycles for TLU trigger low.
  TRIGGER_VETO_SELECT: 0 # Selecting trigger veto: AZ VETO (2), RX FIFO full (1), disabled (0). Set to (2) if SYNC FE is enabled.
  TRIGGER_HANDSHAKE_ACCEPT_WAIT_CYCLES: 5 # TLU trigger minimum length in TLU clock cycles
  DATA_FORMAT: 0 # Select trigger data format: only trigger number (0), only time stamp (1), combined, 15 bit time stamp + 16 bit trigger number (2)
  EN_TLU_VETO: 0 # Assert TLU veto when external veto. Activate this in order to VETO triggers if SYNC FE is enabled.
  TRIGGER_DATA_DELAY: 8 # Depends on the cable length and should be adjusted (run scan/tune_tlu.py)

TDC:
  EN_WRITE_TIMESTAMP: 1 # Writing trigger timestamp
  EN_TRIGGER_DIST: 1 # Measuring trigger to TDC delay with 640MHz clock
  EN_NO_WRITE_TRIG_ERR: 1 # Writing TDC word only if valid trigger occurred
  EN_INVERT_TDC: 0 # Inverting TDC input
  EN_INVERT_TRIGGER: 0 # Inverting trigger input, e.g. for using Test output from EUDET TLU

hardware: # Setup-specific hardware settings
  enable_NTC: True # Only enable if you know you have the correct resistors mounted on the BDAQ board!

electron_conversion: # Charge conversion from DAC to e⁻, typically 8.8 for DC and 13.3 for AC (slightly chip dependent!)
  DC_coupled: 8.8
  AC_coupled: 13.3
calibration: # Setup-specific calibration constants
  bdaq_ntc: # Resistors on BDAQ board for NTC readout
    R16: 1.2e6
    R17: 20e3
    R19: 7.95e3

# Standard analysis settings
# Scans might overwrite these settings if needed.
# Detailed description of parameters in bdaq53/analysis/analysis.py
analysis:
  skip: False # Omit analysis in scans
  create_pdf: True # Create analysis summary pdf
  # module_plotting: True  # Create combined plots for chip in a module
  store_hits: True # store hit table
  cluster_hits: False # store cluster data
  # analyze_tdc: False # analyze TDC words
  # use_tdc_trigger_dist: False # analyze TDC to TRG distance
  # align_method: 0 # how to detect new events
  # chunk_size: 1000000 # scales amount of data in RAM (~150 MB)
  # blocking: True # block main process during analysis