Home CMS Production Clean room MedAustron HEPHY testbeams old
testbeam-RD50-DESY-Apr2024 testbeam-RD50-DESY-Jul2023 testbeam-RD50-CERN-Oct2022 testbeam-DESY-Oct2017 testbeam-DESY-April2017 testbeam-SPS2015 testbeam-SPS2014 testbeam-DESY14 testbeam-SPS12 testbeam-SPS11 testbeam-SPS10 testbeam-SPS09 testbeam-SPS08 LP-TPC
  Belle/Infineon/AIDA testbeam at SPS in Nov 2014, Page 5 of 6  Not logged in ELOG logo
Entry  Wed Nov 19 22:59:24 2014, Hao Yin, Belle SVD, CalibrationRun_004, , , , , Crap 
cooled (see last calibration run)
Latest noise, FIRfilter settings. 
 
Entry  Wed Nov 19 23:15:50 2014, Hao Yin, Belle SVD, HardwareRun_003, , , , , Unknown 
cooled, latest noise, cal, PedestalRun.
Rawmode
Entry  Wed Nov 19 23:31:08 2014, Hao Yin, Belle SVD, HardwareRun_004, , , , , Unknown 
Same as HardwareRun_003 but with ZS.  
Entry  Thu Nov 20 00:52:50 2014, Hao Yin, Belle SVD, FIRRun_002, , , , , Unknown 
cooled with new delay run
Entry  Thu Nov 20 00:54:21 2014, Hao Yin, Belle SVD, PedestalRun_008, , , , , Unknown 
temp see attachment (von flo)
10000
latest fir filter (002)
Entry  Thu Nov 20 00:55:14 2014, Hao Yin, Belle SVD, HardwareRun_007, , , , , Unknown 
temp  cooled see attachment
last noise run(007)
FIRRun_002
Entry  Thu Nov 20 11:13:44 2014, Hao Yin, , HardwareRun_008, 008, , , , Crap 
cooled see attachment in FIRRun_003
PedestalRun_009
CalibrationRun_005
Entry  Thu Nov 20 15:32:33 2014, Hao Yin, , HardwareRun, 010, , , , Crap 
same as hardware run 009

FIFO FULL ERROR starting at ~event 5000
Entry  Thu Nov 20 16:13:18 2014, Hao Yin, Belle SVD, HardwareRun, 011, , , , Crap 
cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode
Entry  Thu Nov 20 22:11:06 2014, Hao Yin, Belle SVD, HardwareRun, 012, , , , Good 
cooled see appendix (FirRun003)

PedestalRun_009

multi 6 Raw Mode
Entry  Fri Nov 21 19:05:27 2014, Hao Yin, Belle SVD, FIRRun_004, , , Fri Nov 21 19:05:23 CET 2014, , Unknown 
New ADC delay scan. cooled, -25 temperature
 
Entry  Fri Nov 21 19:10:09 2014, Hao Yin, Belle SVD, CalibrationRun_006, , , , , Unknown 
cooled, latest ADC delay scan and FIRRun. 
Entry  Fri Nov 21 19:42:36 2014, Hao Yin, , HardwareRun_033, , , , , Good Temp_21-11-14.PNG
L6 are swapped, needs to be corrected later in the offline analysis.

cooled at -25

latest ADC delay and FIRRun
Entry  Fri Nov 21 22:08:32 2014, Hao Yin, , PedestalRun, 013, 10000, , , Unknown 
correct mapping 
cooled -25 °C
L3n deactivated
Entry  Sat Nov 22 15:31:49 2014, Hao Yin, Belle SVD, HardwareRun, 038, 43788, 2014-11-22 15:18:40, , Unknown 
Cooled down to -20
Bias voltage set to +-60V
Pedestal_013 (cooled)
Entry  Sun Nov 23 01:05:43 2014, Hao Yin, Belle SVD, HardwareRun, 039, 20000, 2014-11-22 15:18:40, , Crap 
Cooled down to -20
Bias voltage set to +-80V
Pedestal_013 (cooled)
Entry  Sun Nov 23 01:37:42 2014, Hao Yin, Belle SVD, HardwareRun, 040, 20000, 2014-11-23 01:37:00, , Unknown 
Bias voltage set to +-80V
Pedestal_015 (cooled) 

p, li { white-space: pre-wrap; }
"New" layout with no cooling (CO2 is no more)
Entry  Sun Nov 23 10:32:41 2014, Hao Yin, Belle SVD, PedestalRun, 016, 10000, , , Unknown 
Pedestal Run 
room temperature (30C)
Bias scans planned
Entry  Sun Nov 23 10:51:49 2014, Hao Yin, Belle SVD, HardwareRun, 042, 76863, , , Unknown Temp_23-11-14.PNG
Hardware Run +-40V Bias
Room Temperature
Pedestal 016
Entry  Thu Nov 20 10:22:17 2014, Markus Friedl, Belle SVD, common, , , , , Unknown 

    Some VME errors occured over night
    Optical fiber changed 
    Situation improved

 

    L3n hybrid could not be configured by I2C
    Plugged cable into the former FWDn slot
    Fully
working

 
ELOG V3.1.5-fc6679b