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Entry  Tue May 19 09:31:50 2015, Hao Yin, , , , Noise Test ITA 
Everything works except L3 p-side.

The config file is shown in the following:

### Original Configuration File Name: /home/katsuro/tuxdaq_devel/config/delay_scan.latency_scan.cfg ###
Entry  Tue May 19 10:08:53 2015, Hao Yin, , , , FADC system setup success 
3 FADC. All Channel/APV25 running (except L3 n first and last -> not connected (bonding))

n-side: all connectors

p-side: 0x01: 1, 2, 4 and 0x02, 1 with L3 p and L4 p (Telescope)
Entry  Tue May 19 13:42:04 2015, Hao Yin, , , , L6 Noise inJection Setup P1000702.JPGP1000700.JPGP1000699.JPGP1000703.JPGP1000707.JPG
Test Nr. 1:

RLC between DockBox and Hybrid (both side).

Preliminary Test on L6, but all other sensors are connected.
Entry  Wed May 20 10:12:12 2015, Hao Yin, , , , Ladder RLC test (CMC Injection) 
L5 Ladder Test

folder: /mnt/data/ITA_NOISE_TESTS/Ladder_test

Setup: ladder only, noise injection on one hybrid (injection point = cable between hybrid and junction board, see attachment
Entry  Thu May 21 18:23:22 2015, Hao Yin, , , , Noise Injection LV cable P1000717.JPG
(TestNr. 15)

injecting sin wave into LV at different frequencies to analyse the output frequency and noise ground level after the junction borad.
Entry  Fri May 22 12:01:32 2015, Hao Yin, , , , CMC injection LV 10V 
Comparison w/o filter (LC) connected to -z_n side.

Mateo has the results.
Entry  Mon Nov 30 15:12:19 2015, Hao Yin, , , , FIR_ADC config 
FIR filter and ADC delay test:
ADC delay and FIR filter with and without cooling to reproduce error detected during CERN beam test 2015.
 
Entry  Wed Oct 7 14:23:35 2009, Dieter Uhl, BELLE Upgrade, hybrid, #4, hybrid-pitchadapter pitchadapter4_lower_coat.gifpitchadapter4_lower_coat_opens.gifpitchadapter4_upper_coat.gifpitchadapter4_upper_coat_opens.gif
opens at upper coat
Entry  Wed Oct 7 14:24:06 2009, Dieter Uhl, BELLE Upgrade, hybrid, #5, hybrid-pitchadapter pitchadapter5_lower_coat_opens.gifpitchadapter5_lower_coat.gifpitchadapter5_upper_coat_opens.gifpitchadapter5_upper_coat.gif
shorts at upper coat
Entry  Mon Nov 30 18:32:13 2015, Hao Yin, Belle II, system, ADC Delay Scan Cold,  
ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns)
Entry  Mon Nov 30 15:18:12 2015, Hao Yin, Belle II, module, ADC_DELAY_HOT, ADC delay hot 
ADC delay scan at room temp and 20 min after APV I2C config.

measured values at display in the FIR_HOT cfg file.

17:06 first run 20 min after i2c config.
Entry  Wed May 27 09:30:54 2015, Hao Yin, Belle II, system, CAEN PS Primary side,  P1000776.JPGP1000774.JPGP1000777.JPGP1000780.JPG
Measured Primary side of caen wo load (setup attachment 2 and prelimilary res. attachment 1. )

and with load (attachment 3: Load, att. 4 corresponding circuit scheme)
Entry  Mon May 25 20:27:23 2015, Hao Yin, Belle II, system, Caen PS base line measurements,  P1000760.JPGP1000758.JPG
Baseline noise measurements wo injection.

measure noise in both HV and LV.

wings of APV25 using cmc with 128 strip are visible wo injection. (folder CAEN_PS, run name Noise_xxx.dat).
Entry  Tue May 19 13:23:16 2015, Hao Yin, Belle II, system, Calibration, CalibrationRun001 
PedestalRun001, FIRRun001,

room temperature,

no noise injection
Entry  Tue May 19 10:57:19 2015, Hao Yin, Belle II, system, FIR, FIR filter 
first fir filter run:

# 1:[0x[FADC ID] in hex], 2:[APV25 ChannelNr], 3-10:[fir coef in float]

0x1,0,1.13520608876,-0.0660414994664,-0.0344046528212,-0.0160940592489,-0.0188049576486,-0.00405635272718,0.0022422085805,0.0019532245698
Entry  Mon Nov 30 17:11:17 2015, Hao Yin, Belle II, module, FIRRun001, FIRRun001 aft ADC_HOT 
FirRun 20 min after I2C
Entry  Mon Nov 30 18:44:04 2015, Hao Yin, Belle II, system, FIRRun_Cold,  
ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns)

 
Entry  Mon Nov 30 17:23:51 2015, Hao Yin, Belle II, system, HardwareRun001,  Room_bw_n.pngRoom_bw_p.png
ADC Hot, FIRRun001, PedestalRun001

room temp pedrun

target: BW
Entry  Mon Nov 30 17:47:54 2015, Hao Yin, Belle II, system, HardwareRun002,  Room_-z_n.pngRoom_-z_p.png
ADC Hot, FIRRun001, PedestalRun001

target: -Z

room temp pedrun
Entry  Mon Nov 30 18:49:23 2015, Hao Yin, Belle II, system, Hardware_Cold,  Cold_-z_n.pngCold_-z_p.png
ADC Cold diff to hot: 1-3 adc delay config (max 1.5 ns), FIRRun_Cold_001

target: -Z

 
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